{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,15]],"date-time":"2025-08-15T01:56:51Z","timestamp":1755223011437,"version":"3.43.0"},"reference-count":13,"publisher":"Springer Science and Business Media LLC","issue":"1-2","license":[{"start":{"date-parts":[[2001,5,1]],"date-time":"2001-05-01T00:00:00Z","timestamp":988675200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2001,5,1]],"date-time":"2001-05-01T00:00:00Z","timestamp":988675200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology"],"published-print":{"date-parts":[[2001,5]]},"DOI":"10.1023\/a:1008107104782","type":"journal-article","created":{"date-parts":[[2002,12,22]],"date-time":"2002-12-22T08:17:47Z","timestamp":1040545067000},"page":"29-45","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Designing Run-Time Reconfigurable Systems with JHDL"],"prefix":"10.1007","volume":"28","author":[{"given":"Peter","family":"Bellows","sequence":"first","affiliation":[]},{"given":"Brad","family":"Hutchings","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2001,5,1]]},"reference":[{"key":"320365_CR1","doi-asserted-by":"crossref","unstructured":"P. Bellows and B. Hutchings, \u201cJhdl\u2014An hdl for Reconfigurable Systems, \u201d in Proceedings of IEEE Workshop in FPGAs for Custom Computing Machines, J. Arnold and K.L. Pocek (Eds.), Napa, CA, April 1998, pp. 175\u2013184.","DOI":"10.1109\/FPGA.1998.707895"},{"key":"320365_CR2","unstructured":"P. Bellows, J. Hawkins, S. Hemmert, and B. Hutchings, \u201cA Cad Suite for High-Performance FPGA Design, \u201d in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, J.M. Arnold and K.L. Pocek(Eds.), Napa, CA, April 1999."},{"issue":"1","key":"320365_CR3","doi-asserted-by":"publisher","first-page":"56","DOI":"10.1109\/92.486081","volume":"4","author":"J. Vuillemin","year":"1996","unstructured":"J. Vuillemin, P. Bertin, D. Roncin, M. Shand, H. Touati, and P. Boucard, \u201cProgrammable Active Memories: Reconfigurable Systems Come of Age, \u201d IEEE Transactions on VLSI Systems, vol. 4, no. 1, 1996, pp. 56\u201369.","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"320365_CR4","doi-asserted-by":"crossref","unstructured":"L. Moll and M. Shand, \u201cSystems Performance Measurement on PCI Pamette, \u201d in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, J. Arnold and K.L. Pocek (Eds.), Napa, CA, April 1997, pp. 125\u2013133.","DOI":"10.1109\/FPGA.1997.624612"},{"key":"320365_CR5","doi-asserted-by":"crossref","unstructured":"C. Iseli and E. Sanchez, \u201cSpyder: A Reconfigurable VLIW Processor Using FPGAs, \u201d in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, D.A. Buell and K.L. Pocek (Eds.), Napa, CA, April 1993, pp. 17\u201324.","DOI":"10.1109\/FPGA.1993.279483"},{"key":"320365_CR6","first-page":"176","volume-title":"Field-Programmable Logic: Smart Applications; New Paradigms; and Compliers. 6th In-ternational Workshop on Field-Programmable Logic and Applications","author":"S. Gehring","year":"1996","unstructured":"S. Gehring and S. Ludwig, \u201cThe Trianus System and Its Appli-cation to Custom Computing, \u201d in Field-Programmable Logic: Smart Applications; New Paradigms; and Compliers. 6th In-ternational Workshop on Field-Programmable Logic and Applications, R.W. Hartenstein and M. Glesner (Eds.), Darmstadt, Germany: Springer-Verlag, 1996, pp. 176\u2013184."},{"key":"320365_CR7","doi-asserted-by":"crossref","unstructured":"W. Luk, N. Shirazi, and P.Y.K. Cheung, \u201cCompilation Tools for Run-Time Reconfigurable Design, \u201d in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, J.M. Arnold and K.L. Pocek (Eds.), Napa, CA, April 1997, pp. 56\u201365.","DOI":"10.1109\/FPGA.1997.624605"},{"key":"320365_CR8","doi-asserted-by":"crossref","unstructured":"J. Burns, A. Donlin, J. Hogg, S. Singh, and M de Wit, \u201cA Dy-namic Reconfiguration Run-Time System, \u201d in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, J. Arnold and K.L. Pocek (Eds.), Napa, CA, April 1997, pp. 66\u201375.","DOI":"10.1109\/FPGA.1997.624606"},{"key":"320365_CR9","doi-asserted-by":"crossref","unstructured":"M. Gokhale and E. Gomersoll, \u201cHigh Level Compilation for Fine Grained FPGAs, \u201d in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, J.M. Arnold and K.L. Pocek (Eds.), Napa, CA, April 1997, pp. 165\u2013173.","DOI":"10.1109\/FPGA.1997.624616"},{"issue":"3","key":"320365_CR10","doi-asserted-by":"publisher","first-page":"381","DOI":"10.1109\/92.532038","volume":"4","author":"P. Lysaght","year":"1996","unstructured":"P. Lysaght and J. Stockwood, \u201cA Simulation Tool for Dynami-cally Reconfigurable Field Programmable Gate Arrays, \u201d IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4, no. 3, 1996, pp. 381\u2013390.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"320365_CR11","doi-asserted-by":"crossref","unstructured":"J. Villasenor, B. Schoner, K. Chia, and C. Zapata, \u201cConfigurable Computing Solutions for Automatic Target Recognition, \u201d in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, J. Arnold and K.L. Pocek (Eds.), Napa, CA, April 1996, pp. 70\u201379.","DOI":"10.1109\/FPGA.1996.564749"},{"key":"320365_CR12","volume-title":"Master's thesis, Department of Electrical and Computer Engineering","author":"M. Rencher","year":"1996","unstructured":"M. Rencher, \u201cA Comparison of FPGA Platforms Through SAR\/ATR Algorithm Implementation, \u201d Master's thesis, Department of Electrical and Computer Engineering, Brigham Young University, Provo, Utah, 1996."},{"key":"320365_CR13","doi-asserted-by":"crossref","unstructured":"M. Rencher and B. Hutchings, \u201cAutomated Target Recognition on Splash 2, \u201d in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, J. Arnold and K.L. Pocek (Eds.), Napa, CA, April 1997, pp. 192\u2013200.","DOI":"10.1109\/FPGA.1997.624619"}],"container-title":["Journal of VLSI signal processing systems for signal, image and video technology"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1008107104782.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1023\/A:1008107104782\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1008107104782.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,11]],"date-time":"2025-08-11T09:52:38Z","timestamp":1754905958000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1023\/A:1008107104782"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001,5]]},"references-count":13,"journal-issue":{"issue":"1-2","published-print":{"date-parts":[[2001,5]]}},"alternative-id":["320365"],"URL":"https:\/\/doi.org\/10.1023\/a:1008107104782","relation":{},"ISSN":["0922-5773"],"issn-type":[{"type":"print","value":"0922-5773"}],"subject":[],"published":{"date-parts":[[2001,5]]},"assertion":[{"value":"1 May 2001","order":1,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}