{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,15]],"date-time":"2025-08-15T01:56:45Z","timestamp":1755223005647,"version":"3.43.0"},"reference-count":40,"publisher":"Springer Science and Business Media LLC","issue":"2-3","license":[{"start":{"date-parts":[[2000,3,1]],"date-time":"2000-03-01T00:00:00Z","timestamp":951868800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2000,3,1]],"date-time":"2000-03-01T00:00:00Z","timestamp":951868800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology"],"published-print":{"date-parts":[[2000,3]]},"DOI":"10.1023\/a:1008193422345","type":"journal-article","created":{"date-parts":[[2002,12,22]],"date-time":"2002-12-22T08:17:47Z","timestamp":1040545067000},"page":"181-209","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable Systems"],"prefix":"10.1007","volume":"24","author":[{"given":"Meenakshi","family":"Kaul","sequence":"first","affiliation":[]},{"given":"Ranga","family":"Vemuri","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2000,3,1]]},"reference":[{"key":"255561_CR1","unstructured":"Xilinx Inc., http:\/\/www.xilinx.com. \u201cData Book and Application Notes. \u201d"},{"key":"255561_CR2","unstructured":"Altera Inc., http:\/\/www.altera.com. \u201cData Book and Application Notes. \u201d"},{"key":"255561_CR3","unstructured":"Atmel Inc., http:\/\/www.atmel.com. \u201cData Book and Application Notes. \u201d"},{"key":"255561_CR4","doi-asserted-by":"crossref","unstructured":"B.L. Hutchings and M.J. Wirthlin, \u201cImplementation Approaches for Reconfigurable Logic Applications,\u201d International Workshop on Field-Programmable Logic and Applications, FPL, Springer, 1995, pp. 419\u2013428.","DOI":"10.1007\/3-540-60294-1_136"},{"key":"255561_CR5","doi-asserted-by":"crossref","unstructured":"M. Dorfel and R. Hofmann, \u201cAPrototyping System for High Performance Communication Systems,\u201d IEEE Workshop on Rapid System Prototyping, RSP, IEEE Computer Society Press, 1998, pp. 84\u201388.","DOI":"10.1109\/IWRSP.1998.676673"},{"issue":"6","key":"255561_CR6","doi-asserted-by":"publisher","first-page":"609","DOI":"10.1109\/43.640619","volume":"16","author":"J. Babb","year":"1997","unstructured":"J. Babb, R. Tessier, M. Dahl, S. Hanono, D. Hoki, and A. Agarwal, \u201cLogic Emulation with Virtual Wires,\u201d IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 16, no.6, 1997, pp. 609\u2013626.","journal-title":"IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems"},{"key":"255561_CR7","doi-asserted-by":"crossref","unstructured":"M. Vasilko and D. Ait-Boudaoud, \u201cArchitectural Synthesis for Dynamically Reconfigurable Logic,\u201d International Workshop on Field-Programmable Logic and Applications, FPL, Springer, 1996, pp. 290\u2013296.","DOI":"10.1007\/3-540-61730-2_31"},{"key":"255561_CR8","doi-asserted-by":"crossref","unstructured":"K.M. GajjalaPurna and D. Bhatia, \u201cTemporal Partitioning and Scheduling for Reconfigurable Computing,\u201d FPGAs for Custom Computing Machines, FCCM, IEEE Computer Society Press, 1998, pp. 329\u2013330.","DOI":"10.1109\/FPGA.1998.707939"},{"key":"255561_CR9","doi-asserted-by":"crossref","unstructured":"J. Spillane and H. Owen, \u201cTemporal Partitioning for Partially-Reconfigurable-Field-Programmable Gate,\u201d Reconfigurable Architectures Workshop, RAW in IPPS\/SPDP, Springer, 1998, pp. 37\u201342.","DOI":"10.1007\/3-540-64359-1_670"},{"key":"255561_CR10","doi-asserted-by":"crossref","unstructured":"M. Kaul and R. Vemuri, \u201cOptimal Temporal Partitioning and Synthesis for Reconfigurable Architectures,\u201d Design, Automation and Test in Europe, DATE, IEEE Computer Society Press, 1998, pp. 389\u2013396.","DOI":"10.1109\/DATE.1998.655887"},{"key":"255561_CR11","doi-asserted-by":"crossref","unstructured":"S. Trimberger, \u201cScheduling Designs into a Time-Multiplexed FPGA,\u201d ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA, ACM Press, 1998, pp. 153\u2013160.","DOI":"10.1145\/275107.275135"},{"key":"255561_CR12","doi-asserted-by":"crossref","unstructured":"M. Kaul, R. Vemuri, S. Govindarajan, and I. Ouaiss, \u201cAn Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications,\u201d Design Automation Conference, DAC, IEEE Computer Society Press, 1999, pp. 616\u2013622.","DOI":"10.1145\/309847.310010"},{"issue":"3","key":"255561_CR13","doi-asserted-by":"publisher","first-page":"282","DOI":"10.1109\/92.238442","volume":"1","author":"D.S. Rao","year":"1993","unstructured":"D.S. Rao and F. Kurdahi, \u201cHierarchical Design Space Exploration for a Class of Digital Systems,\u201d IEEE transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, no.3, 1993, pp. 282\u2013294.","journal-title":"IEEE transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"255561_CR14","unstructured":"G.D. Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994."},{"key":"255561_CR15","doi-asserted-by":"crossref","unstructured":"I. Ouaiss, S. Govindarajan, V. Srinivasan, M. Kaul, and R. Vemuri, \u201cAn Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures,\u201d Reconfigurable Architectures Workshop, RAW in IPPS\/SPDP, Springer, 1998, pp. 31\u201336.","DOI":"10.1007\/3-540-64359-1_669"},{"key":"255561_CR16","doi-asserted-by":"crossref","unstructured":"M. Xu and F. Kurdahi, \u201cLayout Driven High Level Synthesis for FPGA Based Architectures,\u201d Design Automation and Test in Europe, DATE, IEEE Computer Society Press, 1998, pp. 446\u2013450.","DOI":"10.1109\/DATE.1998.655896"},{"key":"255561_CR17","unstructured":"M. Wolf, High Performance Compilers for Parallel Computing, Addison-Wesley Publishers, 1996."},{"key":"255561_CR18","unstructured":"S.Y. Kung, VLSI Array Processors, Prentice Hall, 1988."},{"key":"255561_CR19","doi-asserted-by":"crossref","unstructured":"K. Roy-Neogi and C. Sechen, \u201cMultiple FPGA partitioning with performance optimization,\u201d ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA, ACM Press, 1995, pp. 146\u2013152.","DOI":"10.1109\/FPGA.1995.242148"},{"key":"255561_CR20","doi-asserted-by":"crossref","unstructured":"P. Chan, M. Schlag, and J. Zien, \u201cSpectral-Based Multi-Way FPGA Partitioning,\u201d ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA, ACM Press, 1995, pp. 133\u2013139.","DOI":"10.1109\/FPGA.1995.242146"},{"issue":"10","key":"255561_CR21","doi-asserted-by":"publisher","first-page":"1188","DOI":"10.1109\/43.662680","volume":"16","author":"W. Fang","year":"1997","unstructured":"W. Fang and A. Wu, \u201cA Hierarchical Functional Structuring and Partitioning Approach for Multiple-FPGA Implementations,\u201d IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no.10, 1997, pp. 1188\u20131195.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"255561_CR22","doi-asserted-by":"crossref","unstructured":"H. Schmit, L. Arnstein, D. Thomas, and E. Lagnese, \u201cBehavioral Synthesis for FPGA-Based Computing,\u201d FPGAs for Custom Computing Machines, FCCM, IEEE Computer Society Press, 1994, pp. 125\u2013132.","DOI":"10.1109\/FPGA.1994.315591"},{"key":"255561_CR23","doi-asserted-by":"crossref","unstructured":"R.D. Hudson, D.I. Lehn, and P.M. Athanas, \u201cA Run-Time Reconfigurable Engine for Image Interpolation,\u201d FPGAs for Custom Computing Machines, FCCM, IEEE Computer Society Press, 1998, pp. 88\u201395.","DOI":"10.1109\/FPGA.1998.707886"},{"key":"255561_CR24","doi-asserted-by":"crossref","unstructured":"M.J. Wirthlin and B.L. Hutchings, \u201cSequencing Run-Time Reconfigured Hardware with Software,\u201d ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA, ACM Press, 1996, pp. 122\u2013128.","DOI":"10.1109\/FPGA.1996.242439"},{"key":"255561_CR25","doi-asserted-by":"crossref","unstructured":"M. Gokhale and J.M. Stone, \u201cNAPA C: Compiling for Hybrid RISC\/FPGA Architectures,\u201d FPGAs for Custom Computing Machines, FCCM, IEEE Computer Society Press, 1998, pp. 126\u2013135.","DOI":"10.1109\/FPGA.1998.707890"},{"key":"255561_CR26","doi-asserted-by":"crossref","unstructured":"W. Luk, N. Shirazi, and P. Cheung, \u201cAutomating Production of Run-Time Reconfigurable Designs,\u201d FPGAs for Custom Computing Machines, FCCM, IEEE Computer Society Press, 1998, pp. 147\u2013156.","DOI":"10.1109\/FPGA.1998.707892"},{"key":"255561_CR27","doi-asserted-by":"crossref","unstructured":"M. Chu, N. Weaver, K. Sulimma, A. DeHon, and J. Wawrzynek, \u201cObject Oriented Circuit-Generators in Java,\u201d FPGAs for Custom Computing Machines, FCCM, IEEE Computer Society Press, 1998, pp. 158\u2013166.","DOI":"10.1109\/FPGA.1998.707893"},{"key":"255561_CR28","doi-asserted-by":"crossref","unstructured":"M. Kaul and R. Vemuri, \u201cTemporal Partitioning Combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs,\u201d Design Automation and Test in Europe, DATE, IEEE Computer Society Press, 1999, pp. 202\u2013209.","DOI":"10.1109\/DATE.1999.761123"},{"key":"255561_CR29","doi-asserted-by":"crossref","unstructured":"M.J. Wirthlin and B.L. Hutchings, \u201cA Dynamic Instruction Set Computer,\u201d FPGAs for Custom Computing Machines, FCCM, IEEE Computer Society Press, 1995, pp. 99\u2013106.","DOI":"10.1109\/FPGA.1995.477415"},{"key":"255561_CR30","volume-title":"System-Level Codesign of Mixed Hardware-Software Systems","author":"A. Kalavade","year":"1995","unstructured":"A. Kalavade, \u201cSystem-Level Codesign of Mixed Hardware-Software Systems,\u201d Ph.D. Thesis, University of California, Berkeley, 1995."},{"key":"255561_CR31","doi-asserted-by":"crossref","unstructured":"C.H. Gebotys, \u201cOptimal Synthesis of Multichip Architectures,\u201d IEEE ICCAD, IEEE Computer Society Press, 1992, pp. 238\u2013241.","DOI":"10.1109\/ICCAD.1992.279367"},{"key":"255561_CR32","unstructured":"R. Niemann and P. Marwedel, \u201cAn Algorithm for Hardware\/Software Partitioning Using Mixed Integer Linear Programming,\u201d European Design and Test Conference, ED&TC, 1996, pp. 473\u2013479."},{"key":"255561_CR33","doi-asserted-by":"crossref","unstructured":"C.H. Gebotys and M.I. Elmasry, Optimal VLSI Architectural Synthesis, Kluwer Academic Publishers, 1992.","DOI":"10.1007\/978-1-4615-4018-2"},{"issue":"2","key":"255561_CR34","doi-asserted-by":"publisher","first-page":"97","DOI":"10.1287\/ijoc.5.2.97","volume":"5","author":"P. Hansen","year":"1993","unstructured":"P. Hansen, B. Jaumard, and V. Mathon, \u201cConstrained Nonlinear 0-1 Programming,\u201d ORSA Journal of Computing, vol. 5, no.2, 1993, pp. 97\u2013119.","journal-title":"ORSA Journal of Computing"},{"issue":"1","key":"255561_CR35","doi-asserted-by":"publisher","first-page":"156","DOI":"10.1287\/opre.21.1.156","volume":"21","author":"F. Glover","year":"1974","unstructured":"F. Glover and E. Woolsey, \u201cConverting the 0-1 Polynomial Programming Problem to a 0-1 Linear Program,\u201d Operations Research, vol. 21, no.1, 1974, pp. 156\u2013161.","journal-title":"Operations Research"},{"key":"255561_CR36","doi-asserted-by":"crossref","unstructured":"G.K. Wallace, \u201cThe JPEG Still Picture Compression Standard,\u201d ACM Communications, 1991.","DOI":"10.1145\/103085.103089"},{"key":"255561_CR37","doi-asserted-by":"crossref","unstructured":"S. Trimberger, D. Carberry, A. Johnson, and J. Wong, \u201cA Time-Multiplexed FPGA,\u201d FPGAs for Custom Computing Machines, FCCM, IEEE Computer Society Press, 1997, pp. 22\u201328.","DOI":"10.1109\/FPGA.1997.624601"},{"key":"255561_CR38","doi-asserted-by":"crossref","unstructured":"S.M. Scalera and J.R. Vazquez,\u201cThe Design and Implementation of a Context Switching FPGA,\u201d FPGAs for Custom Computing Machines, FCCM, IEEE Computer Society Press, 1998, pp. 78\u201385.","DOI":"10.1109\/FPGA.1998.707884"},{"key":"255561_CR39","unstructured":"Annapolis Micro Systems, Inc., WILDFORCE Reference Manual, Document #1189\u2013Release Notes."},{"key":"255561_CR40","doi-asserted-by":"crossref","unstructured":"Y. Hung and A.C. Parker, \u201cHigh-Level Synthesis with Pin Constraints for Multiple-Chip Designs,\u201d Design Automation Conference, DAC, IEEE Computer Society Press, 1992, pp. 231\u2013234.","DOI":"10.1109\/DAC.1992.227831"}],"container-title":["Journal of VLSI signal processing systems for signal, image and video technology"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1008193422345.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1023\/A:1008193422345\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1008193422345.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,11]],"date-time":"2025-08-11T09:29:57Z","timestamp":1754904597000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1023\/A:1008193422345"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000,3]]},"references-count":40,"journal-issue":{"issue":"2-3","published-print":{"date-parts":[[2000,3]]}},"alternative-id":["255561"],"URL":"https:\/\/doi.org\/10.1023\/a:1008193422345","relation":{},"ISSN":["0922-5773"],"issn-type":[{"type":"print","value":"0922-5773"}],"subject":[],"published":{"date-parts":[[2000,3]]},"assertion":[{"value":"1 March 2000","order":1,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}