{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,25]],"date-time":"2026-03-25T14:28:19Z","timestamp":1774448899499,"version":"3.50.1"},"reference-count":27,"publisher":"Springer Science and Business Media LLC","issue":"1-2","license":[{"start":{"date-parts":[[1998,2,1]],"date-time":"1998-02-01T00:00:00Z","timestamp":886291200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[1998,2,1]],"date-time":"1998-02-01T00:00:00Z","timestamp":886291200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Electronic Testing"],"published-print":{"date-parts":[[1998,2]]},"DOI":"10.1023\/a:1008257118423","type":"journal-article","created":{"date-parts":[[2002,12,22]],"date-time":"2002-12-22T13:47:34Z","timestamp":1040564854000},"page":"41-53","source":"Crossref","is-referenced-by-count":37,"title":["A New Design Method for Self-Checking Unidirectional Combinational Circuits"],"prefix":"10.1007","volume":"12","author":[{"given":"V.V.","family":"Saposhnikov","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Morosov","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vl.V.","family":"Saposhnikov","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"G\u00f6ssel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"154682_CR1","volume-title":"Fault Tolerant and Fault Testable Hardware Design","author":"P.K. Lala","year":"1985","unstructured":"P.K. Lala, Fault Tolerant and Fault Testable Hardware Design, Prentice Hall, Englewood-Cliffs, N.J., 1985."},{"issue":"3","key":"154682_CR2","first-page":"321","volume":"53","author":"V.V. Saposhnikov","year":"1992","unstructured":"V.V. Saposhnikov and Vl.V. Saposhnikov, \u201cSelf-Cheking Checkers for Balansed Codes,\u201d Automation and Remote Control, Vol. 53, No. 3, Part 1, pp. 321\u2013348, 1992.","journal-title":"Automation and Remote Control"},{"key":"154682_CR3","volume-title":"Self-Checking Discrete Circuits","author":"V.V. Saposhnikov","year":"1992","unstructured":"V.V. Saposhnikov and Vl.V. Saposhnikov, Self-Checking Discrete Circuits (in Russian), Energoatomizdat, St. Petersburg, 1992."},{"key":"154682_CR4","unstructured":"R.M. Sedmark, \u201cDesign for Self-Verification. An Approach for Dealing with Testability Problems in VLSI-Based Design,\u201d Proc. 1979, Int. Test Conference, 1979, pp. 112\u2013120."},{"key":"154682_CR5","doi-asserted-by":"crossref","unstructured":"S.K. Gupta and D.K. Pradhan, \u201cCan Concurrent Checkers Help BIST?,\u201d Proc. 1992 International Test Conference, 1992 pp. 140\u2013150.","DOI":"10.1109\/TEST.1992.527814"},{"key":"154682_CR6","doi-asserted-by":"crossref","first-page":"63","DOI":"10.1109\/12.481487","volume":"C-45","author":"S. K. Gupta","year":"1996","unstructured":"S. K. Gupta and D.K. Pradhan, \u201cUtilization of On-line (Concurrent) Checkers during Built-in Self-Test and Vice Versa,\u201d IEEE Trans. Computers, Vol. C-45, pp. 63\u201373, 1996.","journal-title":"IEEE Trans. Computers"},{"issue":"6","key":"154682_CR7","doi-asserted-by":"crossref","first-page":"578","DOI":"10.1109\/TC.1984.1676486","volume":"C-33","author":"E. Fujiwara","year":"1984","unstructured":"E. Fujiwara, N. Muto, and K. Matsuoka, \u201cA Self-Testing Group Parity Prediction Checker and its Use for Built-in-Testing,\u201d IEEE Trans. Comp., Vol. C-33, No. 6, pp. 578\u2013583, 1984.","journal-title":"IEEE Trans. Comp."},{"key":"154682_CR8","doi-asserted-by":"crossref","unstructured":"T.R.N. Rao and E. Fujiwara, Error Control Coding for Computer Systems, Prentice Hall, 1989.","DOI":"10.1016\/B978-0-12-370720-8.50011-8"},{"issue":"2","key":"154682_CR9","first-page":"280","volume":"35","author":"E.S. Sogomonyan","year":"1974","unstructured":"E.S. Sogomonyan, \u201cDesign of Built-in Self-Cheking Monitoring Circuits for Combinational Devices,\u201d Automation and Remote Control, Vol. 35, No. 2, Part 2, pp. 280\u2013289, 1974.","journal-title":"Automation and Remote Control"},{"key":"154682_CR10","unstructured":"E. Fujiwara, \u201cSelf-Testing Group Parity Prediction Checker and its Use for Built-in-Testing,\u201d Proc. 13th Test Symposium Fault Tolerant Computing, Milano, 1983, pp. 146\u2013153."},{"key":"154682_CR11","doi-asserted-by":"crossref","unstructured":"M.J. Ashajee and S.M. Reddy, \u201cOn Totally Self-Checking Checkers for Separable Codes,\u201d IEEE Trans. Comp., Vol. C-16, No. 8, pp. 737\u2013744.","DOI":"10.1109\/TC.1977.1674911"},{"key":"154682_CR12","doi-asserted-by":"crossref","first-page":"186","DOI":"10.1109\/92.285745","volume":"2","author":"K. De","year":"1994","unstructured":"K. De, C. Natarajan, D. Nair, and P. Banerjee, \u201cRSYN: A System for Automated Synthesis of Reliable Multilevel Circuits,\u201d IEEE Transactions on Very Large Integration (VLSI) Systems, No. 2, pp. 186\u2013195, 1994.","journal-title":"IEEE Transactions on Very Large Integration (VLSI) Systems"},{"key":"154682_CR13","unstructured":"A. Morosov, V.V. Saposhnikov, Vl.V. Saposhnikov, and M. G\u00f6ssel, \u201cSelf-Cheking Combinational Circuits with Unidirectionally Independent Outputs,\u201d Technical Report Max-Planck Fault Tolerant Computing Group No. MPI-I-93-605, 1995, to be published in Journal of VLSI."},{"issue":"6","key":"154682_CR14","doi-asserted-by":"crossref","first-page":"878","DOI":"10.1109\/43.229762","volume":"12","author":"N.K. Jha","year":"1993","unstructured":"N.K. Jha and S.-J. Wang, \u201cDesign and Synthesis of Self-Checking VLSI Circuits,\u201d IEEE Transaction CAD, Vol. 12, No. 6, pp. 878\u2013887, 1993.","journal-title":"IEEE Transaction CAD"},{"key":"154682_CR15","first-page":"19","volume":"5","author":"F.Y. Busaba","year":"1994","unstructured":"F.Y. Busaba and P.K. Lala, \u201cSelf-Checking Combinational Circuit Design for Single and Unidirectional Multibit Errors,\u201d JETTA, No. 5, pp. 19\u201328, 1994.","journal-title":"JETTA"},{"key":"154682_CR16","first-page":"267","volume":"4","author":"E.S. Sogomonyan","year":"1993","unstructured":"E.S. Sogomonyan and M. G\u00f6ssel, \u201cDesign of Self-Testing and On-Line Fault Detection Combinational Circuits with Weakly Independent Outputs,\u201d JETTA, No. 4, pp. 267\u2013281, 1993.","journal-title":"JETTA"},{"key":"154682_CR17","doi-asserted-by":"crossref","unstructured":"A. Bogliolo and M. Damiani, \u201cSynthesis of Combinational Circuits with Special Fault-Handling Capabilities,\u201d 13th IEEE Test Symposium, Princeton, N.J., 1995, pp. 454\u2013459.","DOI":"10.1109\/VTEST.1995.512674"},{"issue":"10","key":"154682_CR18","first-page":"1333","volume":"40","author":"E.V. Slabakov","year":"1979","unstructured":"E.V. Slabakov, \u201cDesign of Totally Self-Checking Combinational Circuits by Use of Residual Codes,\u201d Automation and Remote Control, Vol. 40, No. 10, Part 2, pp. 1333\u20131340, 1979.","journal-title":"Automation and Remote Control"},{"key":"154682_CR19","unstructured":"M. G\u00f6ssel and E.S. Sogomonyan, \u201cSelf-Parity Combinational Circuits for Self-Testing, Concurrent Fault Detection and Parity Scan Design,\u201d IFIP Transactions A-42, Computer Science and Technology, VLSI-93, T. Yanagawa and P.A. Ivey (Eds.), North-Holland, 1994, pp. 103\u2013111."},{"key":"154682_CR20","doi-asserted-by":"crossref","DOI":"10.7551\/mitpress\/4317.001.0001","volume-title":"Logic Testing and Design for Testability","author":"H. Fujiwara","year":"1985","unstructured":"H. Fujiwara, Logic Testing and Design for Testability, The MIT Press Cambridge, Massachusetts, London, England, 1985."},{"issue":"5","key":"154682_CR21","first-page":"567","volume":"EC-16","author":"J.P. Roth","year":"1967","unstructured":"J.P. Roth, W.G. Bouricius, and P.R. Schneider, \u201cProgrammed Algorithms to Compute Tests to Detect and Distinguish between Failures in Logic Circuits,\u201d IEEE Trans., Vol. EC-16, No. 5, pp. 567\u2013580, 1967.","journal-title":"IEEE Trans."},{"key":"154682_CR22","volume-title":"Digital Systems Testing and Testable Design","author":"M. Abramovici","year":"1990","unstructured":"M. Abramovici, M. Breuer, and H. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, New York, 1990."},{"key":"154682_CR23","unstructured":"E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, and A. Sangiovanni-Vincentelli, \u201cSIS: A System for Sequential Circuit Synthesis,\u201d Electronics Research Laboratory, Memorandum No. UCB\/ERL M92\/41, 1992."},{"key":"154682_CR24","doi-asserted-by":"crossref","unstructured":"K. De, C. Wu, and P. Banerjee, \u201cReliability Driven Logic Synthesis of Multilevel Circuits,\u201d Int. Symp. on Circuits and Systems, pp. 1105\u20131108, 1992.","DOI":"10.1109\/ISCAS.1992.230286"},{"key":"154682_CR25","doi-asserted-by":"crossref","first-page":"1026","DOI":"10.1109\/TC.1985.1676535","volume":"C-34","author":"B. Bose","year":"1985","unstructured":"B. Bose and D.J. Lin, \u201cSystematic Unidirectional Error-Detecting Codes,\u201d IEEE Trans. Computers, Vol. C-34, pp. 1026\u20131032, 1985.","journal-title":"IEEE Trans. Computers"},{"key":"154682_CR26","unstructured":"M.A. Marouf and A.D. Friedman, \u201cDesign of Self-Checking Checkers for Berger Codes,\u201d Proc. 8th Annual Intern. Conf. on Fault Tolerant Computing, Toulouse, 1978, pp. 179\u2013183."},{"issue":"10","key":"154682_CR27","first-page":"1376","volume":"49","author":"E.S. Sogomonian","year":"1988","unstructured":"E.S. Sogomonian, \u201cReliability of Self-Testing Using Functional Diagnostic Tools,\u201d Automation and Remote Control, Vol. 49, No. 10, Part 2, pp. 1376\u20131380, 1988.","journal-title":"Automation and Remote Control"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1008257118423.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1023\/A:1008257118423\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1008257118423.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:20:59Z","timestamp":1749205259000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1023\/A:1008257118423"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,2]]},"references-count":27,"journal-issue":{"issue":"1-2","published-print":{"date-parts":[[1998,2]]}},"alternative-id":["154682"],"URL":"https:\/\/doi.org\/10.1023\/a:1008257118423","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[1998,2]]}}}