{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:40:08Z","timestamp":1749206408990,"version":"3.41.0"},"reference-count":23,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[1997,12,1]],"date-time":"1997-12-01T00:00:00Z","timestamp":880934400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[1997,12,1]],"date-time":"1997-12-01T00:00:00Z","timestamp":880934400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Electronic Testing"],"published-print":{"date-parts":[[1997,12]]},"DOI":"10.1023\/a:1008262321471","type":"journal-article","created":{"date-parts":[[2002,12,22]],"date-time":"2002-12-22T13:47:34Z","timestamp":1040564854000},"page":"197-209","source":"Crossref","is-referenced-by-count":1,"title":["Testability Properties of Divergent Trees"],"prefix":"10.1007","volume":"11","author":[{"given":"R.D.","family":"Blanton","sequence":"first","affiliation":[]},{"given":"John P.","family":"Hayes","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"146935_CR1","volume-title":"Digital Systems Testing and Testable Design","author":"M. Abramovici","year":"1990","unstructured":"M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, Piscataway, NJ, 1990."},{"issue":"12","key":"146935_CR2","doi-asserted-by":"crossref","first-page":"1061","DOI":"10.1109\/T-C.1973.223651","volume":"22","author":"A.D. Friedman","year":"1973","unstructured":"A.D. Friedman, \u201cEasily Testable Iterative Systems,\u201d IEEE Transactions on Computers, Vol. 22, No.12, pp. 1061\u20131064, Dec. 1973.","journal-title":"IEEE Transactions on Computers"},{"issue":"11","key":"146935_CR3","doi-asserted-by":"crossref","first-page":"842","DOI":"10.1109\/TC.1981.1675715","volume":"30","author":"T. Sridhar","year":"1981","unstructured":"T. Sridhar and J.P. Hayes, \u201cDesign of Easily Testable Bit-sliced Systems,\u201d IEEE Transactions on Computers, Vol. 30, No.11, pp. 842\u2013854, Nov. 1981.","journal-title":"IEEE Transactions on Computers"},{"issue":"11","key":"146935_CR4","doi-asserted-by":"crossref","first-page":"1037","DOI":"10.1109\/TCS.1981.1084934","volume":"28","author":"R. Parthasarathy","year":"1981","unstructured":"R. Parthasarathy and S. Reddy, \u201cA Testable Design of Iterative Logic Arrays,\u201d IEEE Transactions on Circuits and Systems, Vol. 28, No.11, pp. 1037\u20131045, Nov. 1981.","journal-title":"IEEE Transactions on Circuits and Systems"},{"key":"146935_CR5","unstructured":"W. Cheng and J.H. Patel, \u201cTesting in Two-dimensional Iterative Logic Arrays,\u201d Proc. of the 16th International Symposium on Fault-Tolerant Computing, Oct. 1986, pp. 76\u201381."},{"issue":"4","key":"146935_CR6","doi-asserted-by":"crossref","first-page":"573","DOI":"10.1109\/TCAD.1986.1270228","volume":"5","author":"H. Elhuni","year":"1986","unstructured":"H. Elhuni, A. Vergis, and L. Kinney, \u201cC-Testability of Two dimensional Iterative Arrays,\u201d IEEE Transactions on Computer-Aided Design, Vol. 5, No.4, pp. 573\u2013581, Oct. 1986.","journal-title":"IEEE Transactions on Computer-Aided Design"},{"issue":"5","key":"146935_CR7","doi-asserted-by":"crossref","first-page":"640","DOI":"10.1109\/12.53577","volume":"39","author":"C. Wu","year":"1990","unstructured":"C. Wu and P. Cappello, \u201cEasily Testable Iterative Logic Arrays,\u201d IEEE Transactions on Computers, Vol. 39, No.5, pp. 640\u2013652, May 1990.","journal-title":"IEEE Transactions on Computers"},{"issue":"7","key":"146935_CR8","doi-asserted-by":"crossref","first-page":"932","DOI":"10.1109\/43.87603","volume":"10","author":"A. Takach","year":"1991","unstructured":"A. Takach and N. Jha, \u201cEasily Testable Gate-level and DCVS Multipliers,\u201d IEEE Transactions on Computer-Aided Design, Vol. 10, No.7, pp. 932\u2013942, July 1991.","journal-title":"IEEE Transactions on Computer-Aided Design"},{"issue":"2","key":"146935_CR9","doi-asserted-by":"crossref","first-page":"134","DOI":"10.1109\/4.68128","volume":"26","author":"Q. Tong","year":"1991","unstructured":"Q. Tong and N. Jha, \u201cDesign of C-Testable DCVS Binary Array Dividers,\u201d IEEE Journal of Solid-State Circuits, Vol. 26, No.2, pp. 134\u2013141, Feb. 1991.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"146935_CR10","doi-asserted-by":"crossref","unstructured":"A. Chatterjee and J. Abraham, \u201cNCUBE: An Automatic Test Generation Program for Iterative Logic Arrays,\u201d Proc. of International Conference on Computer-Aided Design, Nov. 1988, pp. 428\u2013431.","DOI":"10.1109\/ICCAD.1988.122542"},{"key":"146935_CR11","unstructured":"H. Elhuni and L. Kinney, \u201cTechniques for Testing Hex Connected Systolic Arrays,\u201d Proc. 1986 International Test Conference, Sept. 1986, pp. 1024\u20131033."},{"key":"146935_CR12","unstructured":"J.H. Kim, \u201cOn the Design of Easily Testable and Reconfigurable Systolic Arrays,\u201d Proc. International Conference on Systolic Arrays, 1988, pp. 1024\u20131033."},{"key":"146935_CR13","unstructured":"W.T. Cheng, Testing and Error Detection in Iterative Logic Arrays, Ph.D. thesis, University of Illinois at Urbana-Champaign, 1985."},{"issue":"11","key":"146935_CR14","doi-asserted-by":"crossref","first-page":"875","DOI":"10.1109\/TC.1981.1675718","volume":"30","author":"J. Abraham","year":"1981","unstructured":"J. Abraham and D. Gajski, \u201cDesign of Testable Structures Defined by Simple Loops,\u201d IEEE Transactions on Computers, Vol. 30, No.11, pp. 875\u2013883, Nov. 1981.","journal-title":"IEEE Transactions on Computers"},{"issue":"7","key":"146935_CR15","doi-asserted-by":"crossref","first-page":"752","DOI":"10.1109\/43.55212","volume":"9","author":"D. Bhattacharya","year":"1990","unstructured":"D. Bhattacharya and J.P. Hayes, \u201cDesigning for High-level Test Generation,\u201d IEEE Transactions on Computer-Aided Design, Vol. 9, No.7, pp. 752\u2013766, July 1990.","journal-title":"IEEE Transactions on Computer-Aided Design"},{"issue":"5","key":"146935_CR16","doi-asserted-by":"crossref","first-page":"139","DOI":"10.1007\/BF00137251","volume":"3","author":"F. Lombardi","year":"1992","unstructured":"F. Lombardi and D. Sciuto, \u201cConstant Testability of Combinational Cellular Tree Structures,\u201d Journal of Electronic Testing: Theory and Applications, Vol. 3, No.5, pp. 139\u2013148, May 1992.","journal-title":"Journal of Electronic Testing: Theory and Applications"},{"key":"146935_CR17","doi-asserted-by":"crossref","unstructured":"R.D. Blanton and J.P. Hayes, \u201cEfficient Testing of Tree Circuits,\u201d Proc. of the 23rd International Symposium on Fault-Tolerant Computing, June 1993, pp. 176\u2013185.","DOI":"10.1109\/FTCS.1993.627321"},{"issue":"8","key":"146935_CR18","doi-asserted-by":"crossref","first-page":"950","DOI":"10.1109\/12.536237","volume":"45","author":"R.D. Blanton","year":"1996","unstructured":"R.D. Blanton and J.P. Hayes, \u201cTestability of Convergent Tree Circuits,\u201d IEEE Transactions on Computers, Vol. 45, No.8, pp. 950\u2013963, Aug. 1996.","journal-title":"IEEE Transactions on Computers"},{"key":"146935_CR19","unstructured":"R.D. Blanton and J.P. Hayes, \u201cProperties of the Input Pattern Fault Model,\u201d Proc. of 1997 International Conference on Computer Design, Oct. 1997."},{"key":"146935_CR20","doi-asserted-by":"crossref","unstructured":"W.H. Kautz, \u201cTesting for Faults in Cellular Logic Arrays,\u201d Proc. 8th Symposium on Switching Automata Theory, 1967, pp. 161\u2013174.","DOI":"10.1109\/FOCS.1967.33"},{"key":"146935_CR21","doi-asserted-by":"crossref","unstructured":"D.K. Pradhan and N.R. Kamath, \u201cRTRAM: Reconfigurable Testable Multi-bit RAM Design,\u201d Proc. of 1988 International Test Conference, Sept. 1988, pp. 263\u2013278.","DOI":"10.1109\/TEST.1988.207811"},{"key":"146935_CR22","unstructured":"Texas Instruments, TTL Data Book, Vol. 2, Dallas, Texas, 1985."},{"key":"146935_CR23","unstructured":"R.D. Blanton, Design and Testing of Regular Circuits, Ph.D. thesis, University of Michigan, 1995"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1008262321471.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1023\/A:1008262321471\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1008262321471.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:11:44Z","timestamp":1749204704000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1023\/A:1008262321471"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1997,12]]},"references-count":23,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1997,12]]}},"alternative-id":["146935"],"URL":"https:\/\/doi.org\/10.1023\/a:1008262321471","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[1997,12]]}}}