{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,14]],"date-time":"2025-07-14T02:40:01Z","timestamp":1752460801934,"version":"3.41.2"},"reference-count":52,"publisher":"Springer Science and Business Media LLC","issue":"2-3","license":[{"start":{"date-parts":[[1999,3,1]],"date-time":"1999-03-01T00:00:00Z","timestamp":920246400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[1999,3,1]],"date-time":"1999-03-01T00:00:00Z","timestamp":920246400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Design Automation for Embedded Systems"],"published-print":{"date-parts":[[1999,3]]},"DOI":"10.1023\/a:1008842521805","type":"journal-article","created":{"date-parts":[[2002,12,22]],"date-time":"2002-12-22T11:51:56Z","timestamp":1040557916000},"page":"71-118","source":"Crossref","is-referenced-by-count":16,"title":["Machine-Description Driven Compilers for EPIC and VLIW Processors"],"prefix":"10.1007","volume":"4","author":[{"given":"B. Ramakrishna","family":"Rau","sequence":"first","affiliation":[]},{"given":"Vinod","family":"Kathail","sequence":"additional","affiliation":[]},{"given":"Shail","family":"Aditya","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"205900_CR1","unstructured":"SGS-Thompson Microelectronics. ST18950 User Manual, 1993."},{"key":"205900_CR2","unstructured":"Texas Instruments. TMS320C2x User's Guide, 1993."},{"key":"205900_CR3","unstructured":"Motorola, Inc. DSP56000 24-bit Digital Signal Processor Family Manual, 1995."},{"volume-title":"Code Generation for Embedded Processors","year":"1995","key":"205900_CR4","unstructured":"P. Marwedel and G. Goossens, Eds. Code Generation for Embedded Processors. Kluwer Academic Publishers, Boston, Massachussetts, 1995."},{"key":"205900_CR5","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4757-6422-2","volume-title":"Retargetable Compilers for Embedded Core Processors","author":"C. Liem","year":"1997","unstructured":"C. Liem. Retargetable Compilers for Embedded Core Processors. Kluwer Academic Publishers, Dordrecht, The Netherlands, 1997."},{"key":"205900_CR6","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4757-2570-4","volume-title":"Retargetable Code Generation for Digital Signal Processors","author":"R. Leupers","year":"1997","unstructured":"R. Leupers. Retargetable Code Generation for Digital Signal Processors. Kluwer Academic Publishers, Dordrecht. The Netherlands, 1997."},{"issue":"9","key":"205900_CR7","doi-asserted-by":"crossref","first-page":"18","DOI":"10.1109\/C-M.1981.220595","volume":"14","author":"A. E. Charlesworth","year":"1981","unstructured":"A. E. Charlesworth. An approach to scientific array processing: the architectural design of the AP-120B\/FPS-164 Family. Computer, 14(9): 18-27, 1981.","journal-title":"Computer"},{"key":"205900_CR8","doi-asserted-by":"crossref","unstructured":"B. R. Rau, C. D. Glaeser, and E. M. Greenawalt. Architectural support for the efficient generation of code for horizontal architectures. In Proc. Symposium on Architectural Support for Programming Languages and Operating Systems, pp. 96-99, Palo Alto, March 1982.","DOI":"10.1145\/800050.801832"},{"key":"205900_CR9","doi-asserted-by":"crossref","unstructured":"J. A. Fisher. Very long instruction word architectures and the ELI-512. In Proc. Tenth Annual International Symposium on Computer Architecture, pp. 140-150, Stockholm, Sweden, June 1983.","DOI":"10.1145\/800046.801649"},{"key":"205900_CR10","unstructured":"Texas Instruments. TMS320C62xx CPU and Instruction Set Reference Guide, 1997."},{"key":"205900_CR11","unstructured":"Philips Semiconductors, Trimedia Product Group. Trimedia TM-1 Media Processor Data Book, 1997."},{"issue":"8","key":"205900_CR12","doi-asserted-by":"publisher","first-page":"967","DOI":"10.1109\/12.2247","volume":"C-37","author":"R. P. Colwell","year":"1988","unstructured":"R. P. Colwell, R. P. Nix, J. J. O'Donnell, D. B. Papworth, and P. K. Rodman. A VLIW architecture for a trace scheduling compiler. IEEE Transactions on Computers C-37,8: 967-979, August 1988.","journal-title":"IEEE Transactions on Computers"},{"issue":"1","key":"205900_CR13","doi-asserted-by":"publisher","first-page":"12","DOI":"10.1109\/2.19820","volume":"22","author":"B. R. Rau","year":"1989","unstructured":"B. R. Rau, D. W. L. Yen, W. Yen, and R. A. Towle. The Cydra 5 departmental supercomputer: design philosophies, decisions, and trade-offs. Computer, 22(1): 12-35, January 1989.","journal-title":"Computer"},{"key":"205900_CR14","unstructured":"M. Schlansker, B. R. Rau, S. Mahlke, V. Kathail, R. Johnson, S. Anik, and S. G. Abraham. Achieving High Levels of Instruction-Level Parallelism with Reduced Hardware Complexity. HPL Technical Report HPL-96-120. Hewlett-Packard Laboratories, February 1997."},{"key":"205900_CR15","unstructured":"V. Kathail, M. Schlansker, and B. R. Rau. HPL-PD Architecture Specification: Version 1.1. Technical Report HPL-93-80 (R.1). Hewlett-Packard Laboratories, April 1999."},{"key":"205900_CR16","unstructured":"B. R. Rau, V. Kathail and S. Aditya. Machine-Description Driven Compilers for EPIC Processors. HPL Technical Report HPL-98-40. Hewlett-Packard Laboratories, September 1998."},{"key":"205900_CR17","volume-title":"Formalization and Automatic Derivation of Code Generators","author":"R. G. G. Cattell","year":"1978","unstructured":"R. G. G. Cattell. Formalization and Automatic Derivation of Code Generators. Ph.D. Thesis. Carnegie-Mellon University, Pittsburgh, 1978."},{"key":"205900_CR18","doi-asserted-by":"crossref","unstructured":"R. S. Glanville and S. L. Graham. A new method for compiler code generation. In Proc. 5th Annual ACM Symposium on Principles of Programming Languages, pp. 231-240, 1978.","DOI":"10.1145\/512760.512785"},{"issue":"4","key":"205900_CR19","doi-asserted-by":"publisher","first-page":"573","DOI":"10.1145\/356893.356897","volume":"14","author":"M. Ganapathi","year":"1992","unstructured":"M. Ganapathi, C. N. Fisher, and J. L. Hennessy. Retargetable compiler code generation. ACM Computing Surveys, 14(4): 573-592, December 1992.","journal-title":"ACM Computing Surveys"},{"issue":"3","key":"205900_CR20","doi-asserted-by":"publisher","first-page":"213","DOI":"10.1145\/151640.151642","volume":"1","author":"C.W. Fraser","year":"1992","unstructured":"C.W. Fraser, D. R. Hanson, and T. A. Proebsting. Engineering a simple, efficient code-generator generator. ACM Letters of Programming Languages and Systems, 1(3): 213-226, September 1992.","journal-title":"ACM Letters of Programming Languages and Systems"},{"key":"205900_CR21","unstructured":"R. M. Stallman. Using and porting GNU CC, version 2.4. Free Software Foundation, June 1993."},{"key":"205900_CR22","unstructured":"P. G. Paulin, C. Liem, T. C. May, and S. Sutarwala. FlexWare: a flexible firmware development environment for embedded systems. In Code Generation for Embedded Processors, P. Marwedel and G. Goossens, Eds. Kluwer Academic Publishers, pp. 65-84, 1995."},{"key":"205900_CR23","doi-asserted-by":"crossref","unstructured":"D. Lanneer, J. Van Praet, A. K. Kifli, K. Schoofs, W. Geurts, F. Thoen, and G. Goossens. CHESS: retargetable code generation for embedded DSP processors. In Code Generation for Embedded Processors, P. Marwedel and G. Goossens, Eds. Kluwer Academic Publishers, pp. 85-102, 1995.","DOI":"10.1007\/978-1-4615-2323-9_5"},{"key":"205900_CR24","doi-asserted-by":"crossref","unstructured":"B. Wess. Code generation based on trellis diagrams. In Code Generation for Embedded Processors, P. Marwedel and G. Goossens, Eds. Kluwer Academic Publishers, pp. 188-202, 1995.","DOI":"10.1007\/978-1-4615-2323-9_11"},{"key":"205900_CR25","doi-asserted-by":"crossref","unstructured":"A. Fauth. Beyond tool specific machine descriptions. In Code Generation for Embedded Processors, P. Marwedel and G. Goossens, Eds. Kluwer Academic Publishers, pp. 138-152, 1995.","DOI":"10.1007\/978-1-4615-2323-9_8"},{"key":"205900_CR26","doi-asserted-by":"crossref","unstructured":"S. Hanono and S. Devadas. Instruction selection, resource allocation, and scheduling in the Aviv retargetable code generator. Proc. ACM\/IEEE Design Automation Conference, 1998.","DOI":"10.1145\/277044.277184"},{"issue":"7","key":"205900_CR27","doi-asserted-by":"crossref","first-page":"478","DOI":"10.1109\/TC.1981.1675827","volume":"C-30","author":"J. A. Fisher","year":"1981","unstructured":"J. A. Fisher. Trace scheduling: a technique for global microcode compaction. IEEE Transactions on Computers C-30,7: 478-490, July 1981.","journal-title":"IEEE Transactions on Computers"},{"key":"205900_CR28","doi-asserted-by":"crossref","unstructured":"B. R. Rau and C. D. Glaeser. Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing. In Proc. Fourteenth Annual Workshop on Microprogramming, pp. 183-198, October 1981.","DOI":"10.1145\/1014192.802449"},{"issue":"1\/2","key":"205900_CR29","doi-asserted-by":"publisher","first-page":"181","DOI":"10.1007\/BF01205184","volume":"7","author":"J. C. Dehnert","year":"1993","unstructured":"J. C. Dehnert and R. A. Towle. Compiling for the Cydra 5. The Journal of Supercomputing, 7(1\/2): 181-228, May 1993.","journal-title":"The Journal of Supercomputing"},{"issue":"1\/2","key":"205900_CR30","doi-asserted-by":"publisher","first-page":"51","DOI":"10.1007\/BF01205182","volume":"7","author":"P. G. Lowney","year":"1993","unstructured":"P. G. Lowney, S. M. Freudenberger, T. J. Karzes, W. D. Lichtenstein, R. P. Nix, J. S. O'Donnell, and J. C. Ruttenberg. The Multiflow trace scheduling compiler. The Journal of Supercomputing, 7(1\/2): 51-142, May 1993.","journal-title":"The Journal of Supercomputing"},{"issue":"1\/2","key":"205900_CR31","doi-asserted-by":"publisher","first-page":"229","DOI":"10.1007\/BF01205185","volume":"7","author":"W. W. Hwu","year":"1993","unstructured":"W. W. Hwu, S. A. Mahlke, W. Y. Chen, P. P. Chang, N. J. Warter, R. A. Bringmann, R. G. Ouellette, R. E. Hank, T. Kiyohara, G. E. Haab, J. G. Holm, and D. M. Lavery. The superblock: an effective technique for VLIW and superscalar compilation. The Journal of Supercomputing, 7(1\/2): 229-248, May 1993.","journal-title":"The Journal of Supercomputing"},{"key":"205900_CR32","doi-asserted-by":"crossref","unstructured":"B. R. Rau. Iterative modulo scheduling: an algorithm for software pipelining loops. In Proc. 27th Annual International Symposium on Microarchitecture, pp. 63-74, San Jose, California, November 1994.","DOI":"10.1145\/192724.192731"},{"issue":"1","key":"205900_CR33","doi-asserted-by":"crossref","first-page":"65","DOI":"10.1007\/BF03356743","volume":"24","author":"M. S. Schlansker","year":"1996","unstructured":"M. S. Schlansker, V. Kathail, and S. Anik. Parallelization of control recurrences for ILP processors. International Journal of Parallel Processing, 24(1): 65-102, February 1996.","journal-title":"International Journal of Parallel Processing"},{"key":"205900_CR34","doi-asserted-by":"crossref","unstructured":"M. Schlansker, S. Mahlke, and R. Johnson. Control CPR: A Branch Height Reduction Optimization for EPIC Architectures. Technical Report HPL-1999-34. Hewlett-Packard Lab. March 1999.","DOI":"10.1145\/301618.301659"},{"key":"205900_CR35","volume-title":"Bulldog: A Compiler for VLIW Architectures","author":"J. R. Ellis","year":"1985","unstructured":"J. R. Ellis. Bulldog: A Compiler for VLIW Architectures, The MIT Press, Cambridge, Massachussetts, 1985."},{"key":"205900_CR36","unstructured":"G. Desoli. Instruction Assignment for Clustered VLIW DSP Compilers: A New Approach, HPL Technical Report HPL-98-13. Hewlett-Packard Laboratories, February 1998."},{"key":"205900_CR37","unstructured":"E. Nystrom, and A. E. Eichenberger. Effective Cluster Assignment For Modulo Scheduling, Technical Report. Department of Electrical and Computer Engineering, North Carolina State University, June 1998."},{"issue":"1\/2","key":"205900_CR38","doi-asserted-by":"publisher","first-page":"143","DOI":"10.1007\/BF01205183","volume":"7","author":"G. R. Beck","year":"1993","unstructured":"G. R. Beck, D. W. L. Yen, and T. L. Anderson. The Cydra 5 mini-supercomputer: architecture and implementation. The Journal of Supercomputing, 7(1\/2): 143-180, May 1993.","journal-title":"The Journal of Supercomputing"},{"key":"205900_CR39","doi-asserted-by":"crossref","unstructured":"B. R. Rau. Data flow and dependence analysis for instruction level parallelism, In Fourth International Workshop on Languages and Compilers for Parallel Computing, U. Banerjee, D. Gelernter, A. Nicolau, and D. Padua, Eds. pp. 236-250, Springer-Verlag, 1992.","DOI":"10.1007\/BFb0038668"},{"key":"205900_CR40","doi-asserted-by":"crossref","unstructured":"B. R. Rau, M. S. Schlansker, and P. P. Tirumalai. Code generation schemas for modulo scheduled loops. In Proc. 25th Annual International Symposium on Microarchitecture, pp. 158-169, Portland, Oregon, December 1992.","DOI":"10.1109\/MICRO.1992.697012"},{"issue":"6","key":"205900_CR41","doi-asserted-by":"publisher","first-page":"39","DOI":"10.1109\/2.214441","volume":"26","author":"G. M. Silberman","year":"1993","unstructured":"G. M. Silberman and K. Ebcioglu. An architectural framework for supporting heterogeneous instruction-set architectures. Computer, 26(6): 39-56, June 1993.","journal-title":"Computer"},{"issue":"4","key":"205900_CR42","doi-asserted-by":"publisher","first-page":"376","DOI":"10.1145\/161541.159765","volume":"11","author":"S. A. Mahlke","year":"1993","unstructured":"S. A. Mahlke, W. Y. Chen, R. A. Bringmann, R. E. Hank, W. W. Hwu, B. R. Rau, and M. S. Schlansker. Sentinel scheduling: a model for compiler-controlled speculative execution. ACM Transactions on Computer Systems, 11(4): 376-408, November 1993.","journal-title":"ACM Transactions on Computer Systems"},{"key":"205900_CR43","unstructured":"E. S. Davidson, L. E. Shar, A. T. Thomas, and J. H. Patel. Effective control for pipelined computers. In Proc. COMPCON '90, pp. 181-184, San Francisco, February 1975."},{"key":"205900_CR44","unstructured":"S. Aditya, V. Kathail, and B. R. Rau. Elcor's Machine Description System: Version 3.0, HPL Technical Report HPL-98-128, Hewlett-Packard Laboratories, September 1998."},{"key":"205900_CR45","unstructured":"J. C. Gyllenhaal, W.-m. W. Hwu, and B. R. Rau. HMDES Version 2.0 Specification, Technical Report IMPACT-96-3. University of Illinois at Urbana-Champaign, 1996."},{"key":"205900_CR46","first-page":"92","volume-title":"Proc. 10th Annual Workshop on Microprogramming","author":"M. Tokoro","year":"1977","unstructured":"M. Tokoro, E. Tamura, K. Takase, and K. Tamaru. An approach to microprogram optimization considering resource occupancy and instruction formats. In Proc. 10th Annual Workshop on Microprogramming, pp. 92-108, Niagara Falls, New York, November 1977."},{"key":"205900_CR47","doi-asserted-by":"crossref","unstructured":"W. Schenk. Retargetable code generation for parallel, pipelined processor structures, in Code Generation for Embedded Processors, P. Marwedel and G. Goossens, Eds. pp. 119-135 Kluwer Academic Publishers, 1995.","DOI":"10.1007\/978-1-4615-2323-9_7"},{"key":"205900_CR48","unstructured":"J. C. Gyllenhaal. A Machine Description Language for Compilation, M.S. Thesis, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, 1994."},{"key":"205900_CR49","doi-asserted-by":"crossref","unstructured":"R. Leupers and P. Marwedel. Retargetable generation of code selectors from HDL processor models. In Proc. European Design and Test Conference, pp. 140-144, March 1997.","DOI":"10.1109\/EDTC.1997.582348"},{"key":"205900_CR50","doi-asserted-by":"crossref","unstructured":"G. Hadjiyiannis, S. Hanono, and S. Devadas. ISDL: An instruction set description language for retargetability. In Proc. ACM\/IEEE Design Automation Conference, 1997.","DOI":"10.1145\/266021.266108"},{"key":"205900_CR51","unstructured":"J. C. Gyllenhaal, W.-m. W. Hwu, and B. R. Rau. Optimization of machine descriptions for efficient use. In Proc. 29th Annual IEEE\/ACM International Symposium on Microarchitecture, pp. 349-358, Paris, France, December 1996."},{"key":"205900_CR52","doi-asserted-by":"crossref","unstructured":"A. E. Eichenberger and E. S. Davidson. A reduced multipipeline machine description that preserves scheduling constraints. In Proc. SIGPLAN'96 Conference on Programming Language Design and Implementation, pp. 12-20, Philadelphia, Pennsylvania, May 1996.","DOI":"10.1145\/231379.231386"}],"container-title":["Design Automation for Embedded Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1008842521805.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1023\/A:1008842521805\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1008842521805.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,14]],"date-time":"2025-07-14T02:15:24Z","timestamp":1752459324000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1023\/A:1008842521805"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999,3]]},"references-count":52,"journal-issue":{"issue":"2-3","published-print":{"date-parts":[[1999,3]]}},"alternative-id":["205900"],"URL":"https:\/\/doi.org\/10.1023\/a:1008842521805","relation":{},"ISSN":["0929-5585","1572-8080"],"issn-type":[{"type":"print","value":"0929-5585"},{"type":"electronic","value":"1572-8080"}],"subject":[],"published":{"date-parts":[[1999,3]]}}}