{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,20]],"date-time":"2025-05-20T04:03:01Z","timestamp":1747713781724,"version":"3.40.5"},"reference-count":32,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[1997,12,1]],"date-time":"1997-12-01T00:00:00Z","timestamp":880934400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[1997,12,1]],"date-time":"1997-12-01T00:00:00Z","timestamp":880934400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Heuristics"],"published-print":{"date-parts":[[1997,12]]},"DOI":"10.1023\/a:1009683110027","type":"journal-article","created":{"date-parts":[[2002,12,22]],"date-time":"2002-12-22T22:47:08Z","timestamp":1040597228000},"page":"225-243","source":"Crossref","is-referenced-by-count":1,"title":["Performance-Driven Layer Assignment by Integer Linear Programming and Path-Constrained Hypergraph Partitioning"],"prefix":"10.1007","volume":"3","author":[{"given":"C.-J.","family":"Shi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Vannelli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Vlach","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"2","key":"147018_CR1","doi-asserted-by":"publisher","first-page":"273","DOI":"10.1109\/43.205007","volume":"12","author":"K. Ahn","year":"1993","unstructured":"Ahn, K. and S. Sahni. (1993). \"Constrained Via Minimization,\" IEEE Trans. on Computer-Aided Design 12(2), 273\u2013282.","journal-title":"IEEE Trans. on Computer-Aided Design"},{"issue":"4","key":"147018_CR2","doi-asserted-by":"publisher","first-page":"527","DOI":"10.1109\/31.52754","volume":"37","author":"F. Barahona","year":"1990","unstructured":"Barahona, F. (1990). \"On Via Minimization,\" IEEE Trans. on Circuits and Systems CAS-37(4), 527\u2013530.","journal-title":"IEEE Trans. on Circuits and Systems"},{"issue":"3","key":"147018_CR3","doi-asserted-by":"publisher","first-page":"493","DOI":"10.1287\/opre.36.3.493","volume":"36","author":"F. Barahona","year":"1988","unstructured":"Barahona, F., M. Gr\u00f6tschel, M. J\u00fcnger, and G. Reinelt. (1988). \"An Application of Combinatorial Optimization to Statistical Physics and Circuit Layout Problem,\" Operations Research 36(3), 493\u2013513.","journal-title":"Operations Research"},{"issue":"1","key":"147018_CR4","doi-asserted-by":"publisher","first-page":"67","DOI":"10.1109\/TCAD.1987.1270247","volume":"6","author":"K.C. Chang","year":"1987","unstructured":"Chang, K.C. and D.H.-C. Du. (1987). \"Efficient Algorithms for Layer Assignment Problem,\" IEEE Trans. on Computer-Aided Design CAD-6(1), 67\u201378.","journal-title":"IEEE Trans. on Computer-Aided Design"},{"issue":"5","key":"147018_CR5","doi-asserted-by":"publisher","first-page":"284","DOI":"10.1109\/TCS.1983.1085357","volume":"30","author":"R.W. Chen","year":"1983","unstructured":"Chen, R.W., Y. Kajitani, and S.P. Chan. (1983). \"A Graph-Theoretic via Minimization Algorithm for Two-Layer Printed Boards,\" IEEE Trans. on Circuits and Systems CAS-30(5), 284\u2013299.","journal-title":"IEEE Trans. on Circuits and Systems"},{"issue":"6","key":"147018_CR6","doi-asserted-by":"publisher","first-page":"702","DOI":"10.1109\/43.31525","volume":"8","author":"M.J. Ciesielski","year":"1989","unstructured":"Ciesielski, M.J. (1989). \"Layer Assignment for VLSI Interconnect Delay Minimization,\" IEEE Trans. on Computer-Aided Design CAD-8(6), 702\u2013707.","journal-title":"IEEE Trans. on Computer-Aided Design"},{"key":"147018_CR7","doi-asserted-by":"crossref","unstructured":"Ciesielski, M.J. and E. Kinnen. (1981). \"An Optimum Layer Assignment for Routing in ICs and PCBs.\" Proc. of IEEE\/ACM Design Automation Conf., pp. 733\u2013737. Using the CPLEX Callable Library and CPLEX Mixed Integer Library.(1992). CPLEX Optimization, Inc.","DOI":"10.1109\/DAC.1981.1585439"},{"key":"147018_CR8","doi-asserted-by":"publisher","first-page":"38","DOI":"10.1137\/0402004","volume":"2","author":"H.-A. Choi","year":"1989","unstructured":"Choi, H.-A., K. Nakajima, and C.S. Rim. (1989). \"Graph Bipartition and Via Minimization,\" SIAM J. Disc. Math. 2, 38\u201347.","journal-title":"SIAM J. Disc. Math."},{"key":"147018_CR9","doi-asserted-by":"publisher","first-page":"55","DOI":"10.1063\/1.1697872","volume":"19","author":"W. Elmore","year":"1948","unstructured":"Elmore, W. (1948) \"The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers,\" Journal of Applied Physics 19, 55\u201363.","journal-title":"Journal of Applied Physics"},{"key":"147018_CR10","doi-asserted-by":"crossref","unstructured":"Fiduccia, C.M. and R.M. Mattheyses. (1982). \"A Linear-Time Heuristic for Improving Network Partitions.\" Proc. of IEEE\/ACM Design Automation Conf., pp. 175\u2013181.","DOI":"10.1109\/DAC.1982.1585498"},{"issue":"9","key":"147018_CR11","doi-asserted-by":"publisher","first-page":"845","DOI":"10.1109\/TC.1983.1676333","volume":"32","author":"I.S. Gopal","year":"1983","unstructured":"Gopal, I.S., D. Coppersmith, and C.K. Wong. (1983). \"Optimal Wiring of Movable Terminals,\" IEEE Trans. on Computers, C-32(9), 845\u2013858.","journal-title":"IEEE Trans. on Computers"},{"key":"147018_CR12","doi-asserted-by":"crossref","unstructured":"Hashimoto, A. and J. Stevens. (1971). \"Wire Routing Optimizing Channel Assignment Within Large Aperture.\" Proc. of 8th Design Automation Workshop, pp. 155\u2013169.","DOI":"10.1145\/800158.805069"},{"issue":"4","key":"147018_CR13","doi-asserted-by":"publisher","first-page":"235","DOI":"10.1109\/TCAD.1983.1270041","volume":"2","author":"C.P. Hsu","year":"1983","unstructured":"Hsu, C.P. (1983). \"Minimum-via Topological Routing,\" IEEE Trans. on Computer-Aided Design CAD-2(4), 235\u2013246.","journal-title":"IEEE Trans. on Computer-Aided Design"},{"key":"147018_CR14","doi-asserted-by":"crossref","unstructured":"Joy, D.A. and M.J. Ciesielski. (1992). \"Layer Assignment for Printed Circuit Boards and Integrated Circuits.\" Proceedings of the IEEE, vol. 80, no. 2.","DOI":"10.1109\/5.123300"},{"key":"147018_CR15","doi-asserted-by":"crossref","unstructured":"Kuo,Y.S., T.C. Chern, and W.K. Shih. (1988). \"Fast Algorithm for Optimal Layer Assignment.\" Proc. of IEEE\/ACM Design Automation Conf., pp. 554\u2013559.","DOI":"10.1109\/DAC.1988.14815"},{"key":"147018_CR16","doi-asserted-by":"crossref","unstructured":"McGeer, P.C. and R.K. Brayton. (1989). \"Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network.\" Proc. of IEEE\/ACM Design Automation Conf., pp. 561\u2013567.","DOI":"10.1145\/74382.74476"},{"issue":"11","key":"147018_CR17","doi-asserted-by":"publisher","first-page":"1604","DOI":"10.1109\/12.42135","volume":"38","author":"N.J. Naclerio","year":"1989","unstructured":"Naclerio, N.J., S. Masuda, and K. Nakajima. (1989). \"The Via Minimization Problem is NP-complete,\" IEEE Trans. Computers C-38(11), 1604\u20131608.","journal-title":"IEEE Trans. Computers"},{"key":"147018_CR18","unstructured":"Pinter, R.Y. (1982). \"Optimal Layer Assignment for Interconnect.\" Proc. of IEEE Circuits and Computers Conference, pp. 398\u2013401."},{"key":"147018_CR19","doi-asserted-by":"crossref","unstructured":"Rubinstein, J., P. Penfield, and M.A. Horowitz. (1982). \"Signal Delay in RC Networks,\" IEEE Trans. on Computer-Aided Design, 202\u2013210.","DOI":"10.1109\/TCAD.1983.1270037"},{"issue":"1","key":"147018_CR20","doi-asserted-by":"publisher","first-page":"62","DOI":"10.1109\/12.8730","volume":"38","author":"L.A. Sanchis","year":"1989","unstructured":"Sanchis, L.A. (1989). \"Multiple-Way Network Partitioning,\" IEEE Trans. on Computers 38(1), 62\u201388.","journal-title":"IEEE Trans. on Computers"},{"key":"147018_CR21","doi-asserted-by":"crossref","unstructured":"Shi, C.-J. (1992). \"A Signed Hypergraph Model of Constrained Via Minimization.\" Proc. Second Great Lakes Symp. on VLSI, pp. 159\u2013166.","DOI":"10.1109\/GLSV.1992.218350"},{"key":"147018_CR22","doi-asserted-by":"crossref","unstructured":"Shi, C.-J. (1993a). \"Constrained Via Minimization and Signed Hypergraph Partitioning.\" In D.T. Lee and M. Sarrafzadeh (eds.), Algorithmic Aspects of VLSI Layouts. pp. 337\u2013356. World Scientific Publishing Company.","DOI":"10.1142\/9789812794468_0012"},{"issue":"3","key":"147018_CR23","doi-asserted-by":"publisher","first-page":"467","DOI":"10.1080\/00207219308907125","volume":"75","author":"C.-J. Shi","year":"1993","unstructured":"Shi, C.-J. (1993b). \"Analysis, Sensitivity and Macromodeling of the Elmore Delay in Linear Networks for Performance-Driven VLSI Design,\" International Journal of Electronics 75(3), 467\u2013484.","journal-title":"International Journal of Electronics"},{"key":"147018_CR24","unstructured":"Shi, C.-J., A. Vannelli, and J. Vlach. (1990). \"A Hypergraph Partitioning Approach to the Via Minimization Problem.\" Proc. 1990 Canadian Conf. on VLSI, pp. 2.7.1\u20132.7.8."},{"key":"147018_CR25","unstructured":"Shi, C.-J., and K. Zhang. (1987). \"A Robust Approach to Timing Verification.\" Proc. IEEE Int. Conf. Computer-Aided Design, pp. 56\u201359."},{"key":"147018_CR26","unstructured":"Stevens, K.R. and W.M. vanCleemput. (1979). \"Global Via Minimization in Generalized Routing Environment.\" Proc. IEEE Int. Symp. on Circuits and Systems, pp. 689\u2013692."},{"issue":"7","key":"147018_CR27","doi-asserted-by":"publisher","first-page":"949","DOI":"10.1109\/43.87605","volume":"10","author":"J. Vlach","year":"1991","unstructured":"Vlach, J., J. Barby, A. Vannelli, I. Talkhan, and C.-J. Shi. (1991). \"Group Delay as an Estimate of Delay in Logic,\" IEEE Trans. on Computer-Aided DesignCAD-10(7), 949\u2013953.","journal-title":"IEEE Trans. on Computer-Aided Design CAD"},{"key":"147018_CR28","unstructured":"Weste, N. and K. Eshraghian. (1985). Principles of CMOS VLSI Design: A System Perspective, Addison-Wesley Publishing Company."},{"key":"147018_CR29","volume-title":"Physical Design Automation of VLSI Systems","author":"W.H. Wolf","year":"1988","unstructured":"Wolf, W.H. and A.E. Dunlop. (1988). \"Symbolic Layout and Compaction.\" In B. Breas and M. Lorenzetti (eds.), Physical Design Automation of VLSI Systems. Chap. 6. Menlo Park: Benjamin\/Cummings."},{"issue":"2","key":"147018_CR30","doi-asserted-by":"publisher","first-page":"190","DOI":"10.1109\/31.20197","volume":"36","author":"X.M. Xiong","year":"1989","unstructured":"Xiong, X.M. and E.S. Kuh. (1989). \"A Unified Approach to the Via Minimization Problem,\" IEEE Trans. on Circuits and SystemsCAS-36(2), 190\u2013204.","journal-title":"IEEE Trans. on Circuits and Systems CAS"},{"key":"147018_CR31","doi-asserted-by":"crossref","unstructured":"Yen, S.H.C., D.H.C. Du, and S. Ghanta. (1989). \"Efficient Algorithms for Extracting the KMost Critical Paths in Timing Analysis.\" Proc. of IEEE\/ACM Design Automation Conf., pp. 649\u2013654.","DOI":"10.1145\/74382.74497"},{"issue":"1","key":"147018_CR32","doi-asserted-by":"publisher","first-page":"25","DOI":"10.1109\/TCAD.1982.1269993","volume":"1","author":"T. Yoshimura","year":"1982","unstructured":"Yoshimura, T. and E.S. Kuh. (1982). \"Efficient Algorithms for Channel Routing,\" IEEE Trans. on Computer-Aided DesignCAD-1(1), 25\u201335.","journal-title":"IEEE Trans. on Computer-Aided Design CAD"}],"container-title":["Journal of Heuristics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1009683110027.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1023\/A:1009683110027\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1009683110027.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,19]],"date-time":"2025-05-19T10:49:24Z","timestamp":1747651764000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1023\/A:1009683110027"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1997,12]]},"references-count":32,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1997,12]]}},"alternative-id":["147018"],"URL":"https:\/\/doi.org\/10.1023\/a:1009683110027","relation":{},"ISSN":["1381-1231","1572-9397"],"issn-type":[{"type":"print","value":"1381-1231"},{"type":"electronic","value":"1572-9397"}],"subject":[],"published":{"date-parts":[[1997,12]]}}}