{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,15]],"date-time":"2025-08-15T01:22:56Z","timestamp":1755220976637,"version":"3.43.0"},"reference-count":14,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2001,5,1]],"date-time":"2001-05-01T00:00:00Z","timestamp":988675200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2001,5,1]],"date-time":"2001-05-01T00:00:00Z","timestamp":988675200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["The Journal of Supercomputing"],"published-print":{"date-parts":[[2001,5]]},"DOI":"10.1023\/a:1011132326153","type":"journal-article","created":{"date-parts":[[2002,12,23]],"date-time":"2002-12-23T03:43:03Z","timestamp":1040614983000},"page":"7-22","source":"Crossref","is-referenced-by-count":5,"title":["Formally Analyzed Dynamic Synthesis of Hardware"],"prefix":"10.1007","volume":"19","author":[{"given":"Kong Woei","family":"Susanto","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tom","family":"Melham","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"333395_CR1","unstructured":"R. Boulton, A. Gordon, M. Gordon, J. Harrison, J. Herbert, and J. Van Tassel. Experience with Embedding Hardware Description Languages in HOL. In V. Stavridou, T. F. Melham, and R. T. Boute, eds., Theorem Provers in Circuit Design: Theory, Practice and Experience, pp. 129-156, North-Holland, 1992."},{"key":"333395_CR2","unstructured":"J. Burns, A. Donlin, J. Hogg, S. Singh, and M. de Wit. \u2018A Dynamic Reconfiguration Run-Time System\u2019 In IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, California, April 1997: Preliminary Proceedings, pp. 82-91."},{"key":"333395_CR3","doi-asserted-by":"crossref","unstructured":"Consel and O. Danvy. Tutorial Notes on Partial Evaluation. In ACM Symposium on Principles of Programming languages, 1993, pp. 493-501.","DOI":"10.1145\/158511.158707"},{"key":"333395_CR4","doi-asserted-by":"crossref","unstructured":"P. W. Foulk. \u2018Data-folding in SRAM configurable FPGAs\u2019, In IEEE Workshop on FPGAs for Custom Computing Machines, Napa, California, April 1993, pp. 163-171.","DOI":"10.1109\/FPGA.1993.279467"},{"key":"333395_CR5","unstructured":"P. Hudak, J. Fasel, and J. Peterson. A gentle introduction to Haskell. Technical Report YALEU\/DCS\/RR-901, Yale University, May 1996."},{"key":"333395_CR6","doi-asserted-by":"crossref","unstructured":"T. Kropf, Introduction to Formal Hardware Verification, Springer-Verlag, 1999.","DOI":"10.1007\/978-3-662-03809-3"},{"key":"333395_CR7","unstructured":"W. Luk, N. Shirazi, S. R. Guo, and P. Y. K. Cheung. Compilation Tools for Run-Time Reconfigurable Designs. In K. L. Pocek and J. M. Arnold, eds., IEEE Symposium on FPGAs for Custom Computing Machines 97, IEEE Computer Society Press, 1997."},{"key":"333395_CR8","unstructured":"N. D. Jones, C. K. Gomard, and P. Sestoft. Partial Evaluation and Automatic Program Generation. Prentice Hall International, 1993."},{"key":"333395_CR9","unstructured":"N. McKay and S. Singh. Debugging Techniques for Dynamically Reconfigurable Hardware. In K. L. Pocek and J. M. Arnold, eds., IEEE Symposium on FPGAs for Custom Computing Machines: April 21\u201323, 1999, Napa Valley, California: Proceedings, IEEE Computer Society, 1999."},{"key":"333395_CR10","doi-asserted-by":"crossref","unstructured":"T. F. Melham, Higher Order Logic and Hardware Verification, Cambridge University Press, 1993.","DOI":"10.1017\/CBO9780511569845"},{"key":"333395_CR11","doi-asserted-by":"crossref","unstructured":"S. Singh, J. Hogg, and D. McAuley. Expressing Dynamic Reconfiguration by Partial Evaluation. In Kenneth L. Pocek and Jeffrey Arnold, eds., IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, California, April 1996: Proceedings. IEEE Computer Society Press, 1996, pp. 188-194.","DOI":"10.1109\/FPGA.1996.564830"},{"key":"333395_CR12","doi-asserted-by":"crossref","unstructured":"M. Srivas, H. Rue?, and D. Cyrluk. Hardware Verification using PVS. In Thomas Kropf, ed., Formal Hardware Verification Methods and Systems in Comparison, pp. 156-205. July 1997, Springer Verlag LNCS 1287.","DOI":"10.1007\/3-540-63475-4_4"},{"key":"333395_CR13","doi-asserted-by":"crossref","unstructured":"M. J. Wirthlin and B. L. Hutchings. Improving Functional Density Through Run-Time Constant Propagation. In ACM fifth international symposium on Field-programmable gate arrays, February 1997, Monterey, California, pp. 86-92.","DOI":"10.1145\/258305.258316"},{"key":"333395_CR14","unstructured":"Xilinx. XC6200 FPGA Family Data Sheet. Xilinx Inc., 1995."}],"container-title":["The Journal of Supercomputing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1011132326153.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1023\/A:1011132326153\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1011132326153.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,8]],"date-time":"2025-08-08T05:11:27Z","timestamp":1754629887000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1023\/A:1011132326153"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001,5]]},"references-count":14,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2001,5]]}},"alternative-id":["333395"],"URL":"https:\/\/doi.org\/10.1023\/a:1011132326153","relation":{},"ISSN":["0920-8542","1573-0484"],"issn-type":[{"type":"print","value":"0920-8542"},{"type":"electronic","value":"1573-0484"}],"subject":[],"published":{"date-parts":[[2001,5]]}}}