{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,15]],"date-time":"2025-08-15T01:23:01Z","timestamp":1755220981952,"version":"3.43.0"},"reference-count":21,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2001,6,1]],"date-time":"2001-06-01T00:00:00Z","timestamp":991353600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2001,6,1]],"date-time":"2001-06-01T00:00:00Z","timestamp":991353600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["The Journal of Supercomputing"],"published-print":{"date-parts":[[2001,6]]},"DOI":"10.1023\/a:1011141304485","type":"journal-article","created":{"date-parts":[[2002,12,23]],"date-time":"2002-12-23T03:43:03Z","timestamp":1040614983000},"page":"173-197","source":"Crossref","is-referenced-by-count":0,"title":["On the Boosting of Instruction Scheduling by Renaming"],"prefix":"10.1007","volume":"19","author":[{"given":"L.","family":"Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ted C.","family":"Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"3","key":"337134_CR1","doi-asserted-by":"crossref","first-page":"278","DOI":"10.1109\/12.485567","volume":"45","author":"M. C. Chang","year":"1996","unstructured":"M. C. Chang and F. P. Lai. Efficient exploitation of instruction-level parallelism for superscalar processors by the conjugate register file scheme. IEEE Trans. Comput., 45(3):278-293, 1996.","journal-title":"IEEE Trans. Comput."},{"issue":"1\/2","key":"337134_CR2","doi-asserted-by":"crossref","first-page":"9","DOI":"10.1007\/BF01205181","volume":"7","author":"B. R. Rau","year":"1993","unstructured":"B. R. Rau and J. A. Fisher. Instruction-level parallel processing: history, overview,and perspective. J. Supercomput., 7(1\/2):9-50, 1993.","journal-title":"J. Supercomput."},{"key":"337134_CR3","doi-asserted-by":"crossref","unstructured":"M. S. Schlansker and R. R. Rau. EPIC: Explicitly parallel instruction computing. IEEE Comput., 37-45, 2000.","DOI":"10.1109\/2.820037"},{"key":"337134_CR4","unstructured":"D. I. August, D. A. Connors, S. A. Mahlke, J. W. Sias, K. M. Crozier, B. C. Cheng, P.R. Eaton, Q. B. Olaniran, and W. W. Hwu. Integrated predicated and speculative execution in the IMPACT EPIC architecture. In Proceedings of the 25th Annual International Symposium on Computer Architecture, pp.138-149, 1998."},{"key":"337134_CR5","doi-asserted-by":"crossref","unstructured":"M. S. Lam and R. P. Wilson. Limits of control flow on parallelism. In Proceedings of the 19th Annual International Symposium on Computer Architecture, pp.46-57, 1992.","DOI":"10.1109\/ISCA.1992.753303"},{"key":"337134_CR6","doi-asserted-by":"crossref","unstructured":"S. A. Mahlke, et al. Sentinel scheduling for VLIW and superscalar processors. In Proceedings of the Fifth International Conference on Architectural Support for Programming Languages and Operating System, pp.238-247, 1992.","DOI":"10.1145\/143365.143529"},{"key":"337134_CR7","doi-asserted-by":"crossref","unstructured":"H. Ando et al. Unconstrained speculative execution with predicated state buffering. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, pp.138-149, 1995.","DOI":"10.1145\/223982.224367"},{"key":"337134_CR8","doi-asserted-by":"crossref","unstructured":"M. D. Smith, M. S. Lam,and M. Horowitz. Boosting beyond static scheduling in a superscalar processor. In Proceedings of the 17th Annual International Symposium on Computer Architecture, pp.344-255, 1990.","DOI":"10.1109\/ISCA.1990.134545"},{"key":"337134_CR9","doi-asserted-by":"crossref","unstructured":"S. A. Mahlke, D. C. Lin, and W. Y. Chen et al. Effective compiler support for predicated execution using the hyperblock. In Proceedings of the 25th Annual International Symposium on Microarchitecture, pp.45-54, 1992.","DOI":"10.1109\/MICRO.1992.696999"},{"key":"337134_CR10","doi-asserted-by":"crossref","unstructured":"S. A. Mahlke, R. E. Hank, J. E. McCormick, D. I. August, and W. W. Hwu. A comparison of full and partial predicated execution support for ILP processors. In Proceedings of the 22th Annual International Symposium on Computer Architecture, pp.138-149, 1995.","DOI":"10.1145\/223982.225965"},{"key":"337134_CR11","doi-asserted-by":"crossref","first-page":"478","DOI":"10.1109\/TC.1981.1675827","volume":"C-30","author":"J. A. Fisher","year":"1981","unstructured":"J. A. Fisher. Trace scheduling: a technique for global microcode compaction. IEEE Trans. Comput., C-30:478-490, 1981.","journal-title":"IEEE Trans. Comput."},{"issue":"1\/2","key":"337134_CR12","doi-asserted-by":"crossref","first-page":"229","DOI":"10.1007\/BF01205185","volume":"7","author":"W. W. Hwu","year":"1993","unstructured":"W. W. Hwu et al. The superblock: an effective technique for VLIW and superscalar compilation. J. Supercomput., 7(1\/2):229-248, 1993.","journal-title":"J. Supercomput."},{"key":"337134_CR13","volume-title":"Automatic Construction of Parallel Programs, Algorithms, Software and Hardware for Parallel Computers","author":"V. E. Kotov","year":"1984","unstructured":"V. E. Kotov. Automatic Construction of Parallel Programs, Algorithms, Software and Hardware for Parallel Computers. Springer, Berlin, 1984."},{"issue":"4","key":"337134_CR14","doi-asserted-by":"crossref","first-page":"451","DOI":"10.1145\/115372.115320","volume":"13","author":"R. Cytron","year":"1991","unstructured":"R. Cytron, J. Ferrante, B. Rosen, M. Wegman,and F. Zadeck. Efficiently computing static single assignment and the control dependence graph. ACM Trans. Programm. Languages Syst., 13(4): 451-490, 1991.","journal-title":"ACM Trans. Programm. Languages Syst."},{"key":"337134_CR15","doi-asserted-by":"crossref","unstructured":"P. P. Pineo. An efficient algorithm for the creation of single assignment forms. In Proceedings of the 29th Annual Hawaii International Conference on System Sciences, pp. 213-222, 1996.","DOI":"10.1109\/HICSS.1996.495465"},{"issue":"3","key":"337134_CR16","doi-asserted-by":"crossref","first-page":"367","DOI":"10.1145\/212094.212131","volume":"27","author":"V. H. Allan","year":"1995","unstructured":"V. H. Allan et al. Software pipelining. ACM Comput. Surveys, 27(3): pp.367-432, 1995.","journal-title":"ACM Comput. Surveys"},{"key":"337134_CR17","volume-title":"Computer Architecture: A Quantitative Approach","author":"D. A. Patterson","year":"1996","unstructured":"D. A. Patterson and J. L. Hennessy. Computer Architecture: A Quantitative Approach, 2nd ed. Morgan Maufmann, San Mateo, CA, 1996.","edition":"2nd ed."},{"issue":"6","key":"337134_CR18","doi-asserted-by":"crossref","first-page":"269","DOI":"10.1049\/ip-cdt:19990790","volume":"146","author":"L. Wang","year":"1999","unstructured":"L. Wang and T. C. Yang. Compiler\/hardware co-design for instruction boosting in ILP processors. IEE Proc. Comput. Digit. Technol., 146(6):269-274, 1999.","journal-title":"IEE Proc. Comput. Digit. Technol."},{"issue":"6","key":"337134_CR19","first-page":"278","volume":"143","author":"C. M. Chen","year":"1996","unstructured":"C. M. Chen, C. T. King, and Y. Y. Chen. Branch merging for scheduling concurrent executions of branch operations. IEE Proc. Comput. Digit. Technol., 143(6):278-293, 1996.","journal-title":"IEE Proc. Comput. Digit. Technol."},{"key":"337134_CR20","doi-asserted-by":"crossref","unstructured":"M. Srinivas and A. Nicolau. Analyzing the individual\/combined effects of speculative and guarded execution on a superscalar architecture. In Proceedings of the First Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processing, pp.199-208, 1998.","DOI":"10.1109\/IPPS.1998.669911"},{"issue":"5","key":"337134_CR21","doi-asserted-by":"crossref","first-page":"12","DOI":"10.1109\/40.877947","volume":"20","author":"J. Huck","year":"2000","unstructured":"J. Huck, D. Morris, J. Ross, A. Knies, H. Mulder, and R. Zahir. Introducing the IA-64 architecture. IEEE Micro, 20(5):12-23, 2000.","journal-title":"IEEE Micro"}],"container-title":["The Journal of Supercomputing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1011141304485.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1023\/A:1011141304485\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1011141304485.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,8]],"date-time":"2025-08-08T05:12:04Z","timestamp":1754629924000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1023\/A:1011141304485"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001,6]]},"references-count":21,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2001,6]]}},"alternative-id":["337134"],"URL":"https:\/\/doi.org\/10.1023\/a:1011141304485","relation":{},"ISSN":["0920-8542","1573-0484"],"issn-type":[{"type":"print","value":"0920-8542"},{"type":"electronic","value":"1573-0484"}],"subject":[],"published":{"date-parts":[[2001,6]]}}}