{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:40:04Z","timestamp":1749206404549,"version":"3.41.0"},"reference-count":32,"publisher":"Springer Science and Business Media LLC","issue":"3-4","license":[{"start":{"date-parts":[[2001,6,1]],"date-time":"2001-06-01T00:00:00Z","timestamp":991353600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2001,6,1]],"date-time":"2001-06-01T00:00:00Z","timestamp":991353600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Electronic Testing"],"published-print":{"date-parts":[[2001,6]]},"DOI":"10.1023\/a:1012223614418","type":"journal-article","created":{"date-parts":[[2002,12,23]],"date-time":"2002-12-23T12:42:15Z","timestamp":1040647335000},"page":"311-319","source":"Crossref","is-referenced-by-count":8,"title":["RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems"],"prefix":"10.1007","volume":"17","author":[{"given":"M.B.","family":"Santos","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"F.M.","family":"Gon\u00e7alves","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"I.C.","family":"Teixeira","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.P.","family":"Teixeira","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"358722_CR1","volume-title":"Modelado de Fallos y Estimaci\u00f3n de los Processos de Validaci\u00f3n Funcional de Circuits Digitales Descritos en VHDL Sintetizable","author":"T.R. Alcaide","year":"1996","unstructured":"T.R. Alcaide, \u201cModelado de Fallos y Estimaci\u00f3n de los Processos de Validaci\u00f3n Funcional de Circuits Digitales Descritos en VHDL Sintetizable,\u201d Ph.D. Thesis, Escuela T\u00e9c. Sup. Ing. Industriales, U.P. Madrid, 1996."},{"key":"358722_CR2","doi-asserted-by":"crossref","unstructured":"D. Barclay and J. Armstrong, \u201cA Heuristic Chip-Level Test Generation Algorithm,\u201d in Proc. of the 23rd Design Automation Conference, 1986, pp. 257-262.","DOI":"10.1109\/DAC.1986.1586098"},{"key":"358722_CR3","unstructured":"L. Bening and H. Foster, Principles of Verifiable RTL Design, Kluwer Academic Publishers, 2000."},{"key":"358722_CR4","doi-asserted-by":"crossref","unstructured":"V. Chickermane et al., \u201cAddressing Design for Testability at the Architectural Level,\u201d IEEE Trans. on CAD of Int. Circs. and Syst., Vol. 13,No. 7, 1994.","DOI":"10.1109\/43.293949"},{"key":"358722_CR5","doi-asserted-by":"crossref","unstructured":"Chung-Hsing and D.G. Saab, \u201cA Novel Behavioral Testability Measure,\u201d IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 12,No. 12, December 1993.","DOI":"10.1109\/43.251159"},{"key":"358722_CR6","unstructured":"CMUDSP benchmark (I-99-5, ITC 99 5]), http:\/\/www.ece.cmu.edu\/~lowpower\/benchmarks.html"},{"key":"358722_CR7","unstructured":"S. Davidson, \u201cITC'99 Benchmark Circuits\u2014Preliminary Results, Panel 6 session,\u201d in Proc. ITC, 1999, pp. 1126-1130."},{"key":"358722_CR8","doi-asserted-by":"crossref","unstructured":"Dworak, M.R. Grimaila, S. Lee, L.C. Wang, and M.R. Mercer, \u201cModeling the Probability of Defect Excitation for a Commercial IC with Implications for Stuck-at-Fault-based ATPG Strategies,\u201d in Proc. Int. Test Conf. (ITC), 1999, pp. 1031-1037.","DOI":"10.1109\/TEST.1999.805836"},{"key":"358722_CR9","doi-asserted-by":"crossref","unstructured":"F. Ferrandi, F. Fummi, and D. Sciuto, \u201cImplicit Test Generation for Behavioral VHDL Models,\u201d in Proc. Int. Test Conf. (ITC), 1998, pp. 587-596.","DOI":"10.1109\/TEST.1998.743202"},{"key":"358722_CR10","doi-asserted-by":"crossref","unstructured":"M.H. Gentil, D. Crestani, A.E. Rhalibi, and C. Durant, \u201cA New Testability Measure: Description and Evaluation,\u201d in IEEE VLSI Test Symp. (VTS), 1994, pp. 421-426.","DOI":"10.1109\/VTEST.1994.292279"},{"key":"358722_CR11","doi-asserted-by":"crossref","first-page":"135","DOI":"10.1007\/BF00133499","volume":"2","author":"S. Ghosh","year":"1991","unstructured":"S. Ghosh and T.J. Chakraborty, \u201cOn Behavioral Fault Modeling for Digital Designs,\u201d Journal on Electronic Testing: Theory and Applications, Vol. 2, pp. 135-151, 1991.","journal-title":"Journal on Electronic Testing: Theory and Applications"},{"key":"358722_CR12","unstructured":"X. Gu, K. Kuchcinski, and Z. Peng, \u201cTestability Analysis and Improvement from VHDL Behavioral Specifications,\u201d in Proc. EuroDAC, 1994, pp. 644-649."},{"key":"358722_CR13","unstructured":"G.A. Hayek and C. Robach, \u201cFrom Specification Validation to Hardware Testing: A Unified Method,\u201d in Proc. Int. Test Conf. (ITC), 1996."},{"key":"358722_CR14","doi-asserted-by":"crossref","unstructured":"R.J. Hayne and B.W. Johnson, \u201cBehavioral Fault Modeling in a VHDL Synthesis Environment,\u201d in Proc. Int. Test Conf. (ITC), 1999, pp. 333-340.","DOI":"10.1109\/VTEST.1999.766684"},{"key":"358722_CR15","doi-asserted-by":"crossref","first-page":"577","DOI":"10.1109\/TC.1982.1676054","volume":"C-31-7","author":"Y. Levendel","year":"1982","unstructured":"Y. Levendel and P. Menon, \u201cTest Generation Algorithms for Computer Hardware Description Languages,\u201d IEEE Transactions on Computers, Vol. C-31-7, pp. 577-588, 1982.","journal-title":"IEEE Transactions on Computers"},{"key":"358722_CR16","doi-asserted-by":"crossref","unstructured":"T. Lin and S.Y. Su, The S-algorithm: A Promissing Solution for Systematic Functional Test Generation,\u201d IEEE Trans. on CAD, Vol. CAD-4, pp. 250-263, July 1985.","DOI":"10.1109\/TCAD.1985.1270121"},{"key":"358722_CR17","unstructured":"M.A. Iyer, \u201cHigh Time for High-Level ATPG, Panel 1 session,\u201d in Proc. ITC, 1999, pp. 1113-1119."},{"key":"358722_CR18","doi-asserted-by":"crossref","first-page":"42","DOI":"10.1109\/54.199804","volume":"10","author":"P.C. Maxwell","year":"1993","unstructured":"P.C. Maxwell and R.C. Aitken, \u201cTest Sets and Reject Rates: All Fault Coverages Are Not Created Equal,\u201d in IEEE Design & Test of Comp., Vol. 10, pp. 42-51, Sept. 1993.","journal-title":"IEEE Design & Test of Comp."},{"key":"358722_CR19","doi-asserted-by":"crossref","unstructured":"C. Papachristou and J. Carletta, \u201cTest Synthesis in the Behavioral Domain,\u201d in Proc. Int. Test Conference (ITC), 1995, pp. 693-702.","DOI":"10.1109\/TEST.1995.529899"},{"key":"358722_CR20","doi-asserted-by":"crossref","unstructured":"M.B. Santos, F.M. Gon\u00e7alves, I.C. Teixeira, and J.P. Teixeira, \u201cDefect-Oriented Verilog Fault Simulation of SoC Macros Using a Stratified Fault Sampling Technique,\u201d in Proc. of the IEEE VLSI Test Symp. (VTS), 1999, pp. 326-332.","DOI":"10.1109\/VTEST.1999.766683"},{"key":"358722_CR21","doi-asserted-by":"crossref","unstructured":"M.B. Santos and J.P. Teixeira, \u201cDefect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL,\u201d in Proc. of the Design Autom. and Test in Europe (DATE) Conf., 1999, pp. 549-553.","DOI":"10.1109\/DATE.1999.761181"},{"key":"358722_CR22","unstructured":"S. Sengupta, S. Kundu, S. Chakravarty, P. Parvathala, R. Galivanche, G. Kosonocky, M. Rodgers, and T.M. Mak, \u201cDefect-Based Test: A Key Enabler for Success Migration to Structural Test,\u201d Intel Technology Journal, Q1'99, available at http:\/\/www.developer.intel.com\/ITJ, 1999."},{"issue":"6","key":"358722_CR23","doi-asserted-by":"crossref","first-page":"13","DOI":"10.1109\/MDT.1985.294793","volume":"2","author":"J.P. Shen","year":"1985","unstructured":"J.P. Shen, W. Maly, and F.J. Ferguson, \u201cInductive Fault Analysis of MOS Integrated Circuits,\u201d IEEE Design and Test of Computers, Vol. 2,No. 6, pp. 13-26, December 1985.","journal-title":"IEEE Design and Test of Computers"},{"issue":"10","key":"358722_CR24","doi-asserted-by":"crossref","first-page":"1286","DOI":"10.1109\/43.541448","volume":"15","author":"J.J.T. Sousa","year":"1996","unstructured":"J.J.T. Sousa, F.M. Gon\u00e7alves, J.P. Teixeira, C. Marzocca, F. Corsi, and T.W. Williams, \u201cDefect Level Evaluation in an IC Design Environment,\u201d IEEE Trans. on CAD, Vol. 15,No. 10, pp. 1286-1293, 1996.","journal-title":"IEEE Trans. on CAD"},{"key":"358722_CR25","doi-asserted-by":"crossref","unstructured":"K. Thearling and J. Abraham, \u201cAn Easily Functional Level Testability Measure,\u201d in IEEE Int. Test Conference (ITC), 1989, pp. 381-390.","DOI":"10.1109\/TEST.1989.82322"},{"key":"358722_CR26","doi-asserted-by":"crossref","unstructured":"Y. Le Traon and C. Robach, \u201cFrom Hardware to Software Testability,\u201d in Proc Int. Test Conference (ITC), 1995, pp. 710-719.","DOI":"10.1109\/TEST.1995.529901"},{"key":"358722_CR27","unstructured":"TORCH benchmark (I-99-4, ITC 99 5]), http:\/\/www-flash.stanford.edu:80\/torch\/torchspec\/"},{"key":"358722_CR28","doi-asserted-by":"crossref","unstructured":"M. Vahid and A. Orailoglu, \u201cTestability Metrics for Synthesis of Self-Testable Designs and Effective Test Plans,\u201d in Proc. IEEE VLSI Test Symp. (VTS), 1995, pp. 170-175.","DOI":"10.1109\/VTEST.1995.512633"},{"key":"358722_CR29","doi-asserted-by":"crossref","unstructured":"J.R. Wallack and R. Dandapani, \u201cCoverage Metrics for Functional Tests,\u201d in Proc. IEEE VLSI Test Symp. (VTS), 1994, pp. 176-181.","DOI":"10.1109\/VTEST.1994.292317"},{"key":"358722_CR30","doi-asserted-by":"crossref","unstructured":"L.C. Wang, R. Mercer, and T.W. Williams, \u201cOn the Decline of Testing Efficiency as Fault Coverage Approaches 100%,\u201d in Proc. IEEE VLSI Test Symp. (VTS), 1995, pp. 74-83.","DOI":"10.1109\/VTEST.1995.512620"},{"key":"358722_CR31","doi-asserted-by":"crossref","unstructured":"P.C. Ward and J.R. Armstrong, \u201cBehavioral Fault Simulation in VHDL,\u201d in Proc. 27th. ACM\/IEEE Design Automation Conf. (DAC), 1990, pp. 587-593.","DOI":"10.1145\/123186.123411"},{"key":"358722_CR32","doi-asserted-by":"crossref","unstructured":"Y. Zorian, E. van Marinissen, and S. Dye, \u201cTesting Embedded-Core Based System Chips,\u201d in Proc. Int. Test Conf. (ITC), 1998, pp. 130-143.","DOI":"10.1109\/TEST.1998.743146"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1012223614418.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1023\/A:1012223614418\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1012223614418.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:09:53Z","timestamp":1749204593000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1023\/A:1012223614418"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001,6]]},"references-count":32,"journal-issue":{"issue":"3-4","published-print":{"date-parts":[[2001,6]]}},"alternative-id":["358722"],"URL":"https:\/\/doi.org\/10.1023\/a:1012223614418","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2001,6]]}}}