{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:40:07Z","timestamp":1749206407994,"version":"3.41.0"},"reference-count":21,"publisher":"Springer Science and Business Media LLC","issue":"3-4","license":[{"start":{"date-parts":[[2001,6,1]],"date-time":"2001-06-01T00:00:00Z","timestamp":991353600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2001,6,1]],"date-time":"2001-06-01T00:00:00Z","timestamp":991353600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Electronic Testing"],"published-print":{"date-parts":[[2001,6]]},"DOI":"10.1023\/a:1012275631257","type":"journal-article","created":{"date-parts":[[2002,12,23]],"date-time":"2002-12-23T12:42:15Z","timestamp":1040647335000},"page":"321-330","source":"Crossref","is-referenced-by-count":4,"title":["Sequential Circuit Test Generation Using a Symbolic\/Genetic Hybrid Approach"],"prefix":"10.1007","volume":"17","author":[{"given":"Franco","family":"Fummi","sequence":"first","affiliation":[]},{"given":"Marco","family":"Boschini","sequence":"additional","affiliation":[]},{"given":"Xiaoming","family":"Yu","sequence":"additional","affiliation":[]},{"given":"Elizabeth M.","family":"Rudnick","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"358723_CR1","doi-asserted-by":"crossref","unstructured":"W.-T. Cheng, \u201cThe BACK Algorithm for Seguential Test Generation,\u201d in Proc. Int. Conf. Computer Design, Oct. 1988, pp. 66-69.","DOI":"10.1109\/ICCD.1988.25661"},{"issue":"4","key":"358723_CR2","doi-asserted-by":"crossref","first-page":"19","DOI":"10.1007\/BF00971937","volume":"10","author":"H. Cho","year":"1993","unstructured":"H. Cho, S. Jeong, F. Somenzi, and C. Pixley, \u201cSynchronizing Sequences and Symbolic Traversal Techniques in Test Generation,\u201d Journal of Electronic Testing: Theory and Applications, Vol. 10,No. 4, pp. 19-31, 1993.","journal-title":"Journal of Electronic Testing: Theory and Applications"},{"key":"358723_CR3","doi-asserted-by":"crossref","unstructured":"F. Corno, J.H. Patel, E.M. Rudnick, M. Sonza Reorda, and R. Vietti, \u201cEnhancing Topological ATPG with High-Level Information and Symbolic Techniques,\u201d in Proc. Int. Conf. Computer Design, Oct. 1998.","DOI":"10.1109\/ICCD.1998.727096"},{"issue":"8","key":"358723_CR4","doi-asserted-by":"crossref","first-page":"991","DOI":"10.1109\/43.511578","volume":"15","author":"F. Corno","year":"1996","unstructured":"F. Corno, P. Prinetto, M. Rebaudengo, and M. Sonza Reorda, \u201cA Genetic Algorithm for Automatic Test Pattern Generation for Large Synchronous Sequential Circuits,\u201d IEEE Trans. Computer Aided Design, Vol. 15,No. 8, pp. 991-1000, August 1996.","journal-title":"IEEE Trans. Computer Aided Design"},{"key":"358723_CR5","doi-asserted-by":"crossref","unstructured":"F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, and G. Squillero, \u201cA New Aproach for Initialization Sequences Computation for Synchronous Sequential Circuits,\u201d in Proc. IEEE Int. Conf. Computer Design, 1997, pp. 381-386.","DOI":"10.1109\/ICCD.1997.628898"},{"key":"358723_CR6","unstructured":"D. Corvino, I. Epicoco, F. Ferrandi, F. Fummi, and D. Sciuto, \u201cAutomatic VHDL Restructuring for RTL Synthesis Optimization and Testability Improvement,\u201d in Proc. IEEE Int. Conf. Computer Design, 1998, pp. 587-596."},{"issue":"7","key":"358723_CR7","doi-asserted-by":"crossref","first-page":"760","DOI":"10.1109\/43.851991","volume":"19","author":"F. Ferrandi","year":"2000","unstructured":"F. Ferrandi, F. Fummi, E. Macii, M. Poncino, and D. Sciuto, \u201cSymbolic Optimization of Interacting Controlers Based on Redundancy Identification and Removal,\u201d IEEE Trans. Computer-Aided Design, Vol. 19,No. 7, pp. 760-772, July 2000.","journal-title":"IEEE Trans. Computer-Aided Design"},{"key":"358723_CR8","volume-title":"High-Level Synthesis, Introduction to Chip and System Design","author":"D.D. Gajski","year":"1992","unstructured":"D.D. Gajski, N.D. Dutt, and A.C-H. Wu, High-Level Synthesis, Introduction to Chip and System Design. Dordrecht: Kluwer Academic Publishers, 1992."},{"issue":"3","key":"358723_CR9","doi-asserted-by":"crossref","first-page":"215","DOI":"10.1109\/TC.1981.1675757","volume":"C-30","author":"P. Goel","year":"1981","unstructured":"P. Goel, \u201cAn Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits\u201d, IEEE Trans. Computers, Vol. C-30,No. 3, pp. 215-222, March 1981.","journal-title":"IEEE Trans. Computers"},{"key":"358723_CR10","doi-asserted-by":"crossref","unstructured":"M.S. Hsiao, M.M. Rudnick, and J.H. Patel, \u201cAlternating Strategies for Sequential Circuit ATPG,\u201d in Proc. European Design and Test Conf., 1996, pp. 368-374.","DOI":"10.1109\/EDTC.1996.494327"},{"key":"358723_CR11","doi-asserted-by":"crossref","unstructured":"M.S. Hsiao, E.M. Rudnick, and J.H. Patel, \u201cSequential Circuit Test Generation Using Dynamic State Traversal,\u201d in Proc. European Design and Test Conf., 1997, pp. 22-28.","DOI":"10.1109\/EDTC.1997.582325"},{"issue":"3","key":"358723_CR12","doi-asserted-by":"crossref","first-page":"239","DOI":"10.1109\/43.700722","volume":"17","author":"M.S. Hsiao","year":"1998","unstructured":"M.S. Hsiao, E.M. Rudnick, and J.H. Patel, \u201cApplication of Genetically Engineered Finite-State-Machine Sequences to Sequential Circuit ATPG\u201d, IEEE Trans. Computer-Aided Design, Vol. 17,No. 3, pp. 239-254, March 1998.","journal-title":"IEEE Trans. Computer-Aided Design"},{"key":"358723_CR13","unstructured":"M. Keim, N. Drechsler, and B. Becker, \u201cCombining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits,\u201d ASP Design Automation Conf., Jan. 1999."},{"issue":"10","key":"358723_CR14","doi-asserted-by":"crossref","first-page":"1081","DOI":"10.1109\/43.7807","volume":"7","author":"H. T. Ma","year":"1988","unstructured":"H.-K. T. Ma, S. Devadas, A.R. Newton, and A. Sangiovanni-Vincentelli, \u201cTest Generation for Sequential Circuits,\u201d IEEE Trans. Computer-Aided Design, Vol. 7,No. 10, pp. 1081-1093, Oct. 1988.","journal-title":"IEEE Trans. Computer-Aided Design"},{"key":"358723_CR15","doi-asserted-by":"crossref","unstructured":"R. Marlett, \u201cAn Effective Test Generation System for Sequential Circuits,\u201d in Proc. Design Automation Conf., June 1986, pp. 250-256.","DOI":"10.1109\/DAC.1986.1586097"},{"key":"358723_CR16","doi-asserted-by":"crossref","unstructured":"T.M. Niermann and J.H. Patel, \u201cHITEC: A Test Generation Package for Sequential Circuits\u201d, in Proc. European Conf. Design Automation (EDAC), Feb. 1991, pp. 214-218.","DOI":"10.1109\/EDAC.1991.206393"},{"key":"358723_CR17","doi-asserted-by":"crossref","unstructured":"E.M. Rudnick and J.H. Patel, \u201cCombining Deterministic and Genetic approaches for Sequential Circuit Test Generation,\u201d in Proc. Design Automation Conf., June 1995, pp. 183-188.","DOI":"10.1109\/DAC.1995.250087"},{"issue":"9","key":"358723_CR18","doi-asserted-by":"crossref","first-page":"1034","DOI":"10.1109\/43.658571","volume":"16","author":"E.M. Rudnick","year":"1997","unstructured":"E.M. Rudnick, J.H. Patel, G.S. Greenstein, and T.M. Niermann, \u201cA Genetic Algorithm Framework for Test Generation,\u201d IEEE Trans. computer-Aided Design, Vol. 16,No. 9, pp. 1034-1044, Sept. 1997.","journal-title":"IEEE Trans. computer-Aided Design"},{"key":"358723_CR19","unstructured":"D.G. Saab, Y.G. Saab, and J.A. Abraham, \u201cIterative [Simulation-Based Genetics + Deterministic Techniques] = Complete ATPG,\u201d in Proc. Int. Conf. Computer-Aided Design, Nov. 1994, pp. 40-43."},{"issue":"10","key":"358723_CR20","doi-asserted-by":"crossref","first-page":"1278","DOI":"10.1109\/43.541447","volume":"15","author":"D.G. Saab","year":"1996","unstructured":"D.G. Saab, Y.G. Saab, and J.A. Abraham, \u201cAutomatic Test Vector Cultivation for Sequential VLSI circuits Using Genetic Algorithms,\u201d IEEE Trans. Computer-Aided Design, Vol. 15,No. 10, pp. 1278-1285, Oct. 1996.","journal-title":"IEEE Trans. Computer-Aided Design"},{"key":"358723_CR21","unstructured":"F. Somenzi, CUDD: CU decision diagram package, version 2.2.0. Department of Electrical and Computer Engineering, University of Colorado at Boulder, 1998."}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1012275631257.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1023\/A:1012275631257\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1012275631257.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:12:41Z","timestamp":1749204761000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1023\/A:1012275631257"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001,6]]},"references-count":21,"journal-issue":{"issue":"3-4","published-print":{"date-parts":[[2001,6]]}},"alternative-id":["358723"],"URL":"https:\/\/doi.org\/10.1023\/a:1012275631257","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2001,6]]}}}