{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:46:04Z","timestamp":1759146364083,"version":"3.41.0"},"reference-count":15,"publisher":"Springer Science and Business Media LLC","issue":"5","license":[{"start":{"date-parts":[[2001,10,1]],"date-time":"2001-10-01T00:00:00Z","timestamp":1001894400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2001,10,1]],"date-time":"2001-10-01T00:00:00Z","timestamp":1001894400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Electronic Testing"],"published-print":{"date-parts":[[2001,10]]},"DOI":"10.1023\/a:1012751118746","type":"journal-article","created":{"date-parts":[[2002,12,23]],"date-time":"2002-12-23T14:27:29Z","timestamp":1040653649000},"page":"395-408","source":"Crossref","is-referenced-by-count":5,"title":["Frequency Response Verification of Analog Circuits Using Global Optimization Techniques"],"prefix":"10.1007","volume":"17","author":[{"given":"Suresh","family":"Seshadri","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jacob A.","family":"Abraham","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"381055_CR1","unstructured":"P. Allen and D. Holberg, CMOS Analog Circuit Design, Holt, Rinehart and Winston, 1987."},{"issue":"3","key":"381055_CR2","doi-asserted-by":"crossref","first-page":"417","DOI":"10.1109\/92.406999","volume":"3","author":"B.A.A. Antao","year":"1995","unstructured":"B.A.A. Antao and A.J. Brodersen, \u201cBehavioral Simulation for Analog System Design Verification,\u201d IEEE Trans. VLSI Systems, vol. 3,no. 3, pp. 417-429, Sept. 1995.","journal-title":"IEEE Trans. VLSI Systems"},{"key":"381055_CR3","doi-asserted-by":"crossref","unstructured":"B.A. Antao and F.M. El-Turky, \u201cAutomatic Analog Model Generation For Behavioral Simulation,\u201d in Proc. IEEE Custom Integ. Circuits Conf., 1992, pp. 12.2.1-12.2.4.","DOI":"10.1109\/CICC.1992.591289"},{"key":"381055_CR4","doi-asserted-by":"crossref","unstructured":"A. Balivada, Y. Hoskote, and J.A. Abraham, \u201cVerification of Transient Response of Linear Analog Circuits,\u201d in Proc. IEEE VTS, 1995, pp. 42-47.","DOI":"10.1109\/VTEST.1995.512615"},{"issue":"2","key":"381055_CR5","first-page":"17","volume":"1","author":"M. Bjorkman","year":"1999","unstructured":"M. Bjorkman and K. Holmstrom, \u201cGlobal Optimization Using the Direct Algorithm in Matlab,\u201d Advanced Modeling and Optimization, vol. 1,no. 2, pp. 17-37, 1999.","journal-title":"Advanced Modeling and Optimization"},{"key":"381055_CR6","unstructured":"O. Coudert, C. Berthet, and J. Madre, \u201cVerification of Sequential Machines Using Boolean Functional Vectors,\u201d in VLSI Design Methods II, L. Claesen (Ed.), 1990, pp. 179-196."},{"key":"381055_CR7","doi-asserted-by":"crossref","unstructured":"A. Ghosh and R. Vemuri, \u201cFormal Verification of Synthesized Analog Designs,\u201d in Proc. IEEE Int. Conf. Computer Design, 1999, pp. 40-45.","DOI":"10.1109\/ICCD.1999.808362"},{"key":"381055_CR8","doi-asserted-by":"crossref","unstructured":"L. Hedrich and E. Barke, \u201cA Formal Approach to Nonlinear Analog Circuit Verification,\u201d in Proc. IEEE Conf. CAD, 1995, pp. 123-127.","DOI":"10.1109\/ICCAD.1995.480002"},{"key":"381055_CR9","doi-asserted-by":"crossref","unstructured":"B. Kaminska, K. Arabi, I. Bell, J.L. Huertas, B. Kim, A. Rueda, and M. Soma, \u201cAnalog and Mixed-Signal Benchmark Circuits\u2014First release,\u201d in Proc. IEEE ITC, 1997, pp. 183-190. www.ee.washington.edu\/mad\/madtest.html","DOI":"10.1109\/TEST.1997.639612"},{"key":"381055_CR10","doi-asserted-by":"crossref","unstructured":"E.W.Y Liu, H.C. Chang, A.L. Sangiovanni-Vincentelli, \u201cAnalog System Verification in the Presence of Parasitics using Behavioral Simulation,\u201d in Proc. Design Automation Conf., 1993, pp. 159-162.","DOI":"10.1145\/157485.164648"},{"key":"381055_CR11","doi-asserted-by":"crossref","unstructured":"P. Mandal and V. Visvanathan, \u201cMacromodeling of the AC Characteristics of CMOS Op-Amps,\u201d in Proc. IEEE International Conference CAD, 1993, pp. 334-340.","DOI":"10.1109\/ICCAD.1993.580078"},{"key":"381055_CR12","doi-asserted-by":"crossref","unstructured":"M.C. Mcfarland, \u201cFormal Verification of Sequential Hardware: A Tutorial,\u201d IEEE Trans. CAD, vol. 12,no. 5, May 1993.","DOI":"10.1109\/43.277609"},{"key":"381055_CR13","unstructured":"Meta-Software, HSPICE user's manual, Release 1998.2, July 1998."},{"key":"381055_CR14","unstructured":"S. Seshadri, \u201cVerification of Analog Circuits,\u201d Master's Thesis, The University of Texas at Austin, May, 2000."},{"key":"381055_CR15","unstructured":"S. Seshadri and J.A. Abraham, \u201cFrequency Response Verification of Analog Circuits using Global Optimization Techniques,\u201d in Proc. Intl. Mixed-Signal Test Workshop, June 2000."}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1012751118746.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1023\/A:1012751118746\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1012751118746.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:12:10Z","timestamp":1749204730000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1023\/A:1012751118746"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001,10]]},"references-count":15,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2001,10]]}},"alternative-id":["381055"],"URL":"https:\/\/doi.org\/10.1023\/a:1012751118746","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2001,10]]}}}