{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,15]],"date-time":"2025-08-15T01:22:41Z","timestamp":1755220961178,"version":"3.43.0"},"reference-count":38,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2002,2,1]],"date-time":"2002-02-01T00:00:00Z","timestamp":1012521600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2002,2,1]],"date-time":"2002-02-01T00:00:00Z","timestamp":1012521600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["The Journal of Supercomputing"],"published-print":{"date-parts":[[2002,2]]},"DOI":"10.1023\/a:1013679420784","type":"journal-article","created":{"date-parts":[[2002,12,23]],"date-time":"2002-12-23T17:11:47Z","timestamp":1040663507000},"page":"161-177","source":"Crossref","is-referenced-by-count":1,"title":["Configuring of Algorithms in Mapping into Hardware"],"prefix":"10.1007","volume":"21","author":[{"given":"Toomas P.","family":"Plaks","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"392095_CR1","doi-asserted-by":"crossref","unstructured":"R. Bittner and P. Athanas. Wormhole run-time reconfiguration. In FPGA '97: ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, ACM, 1997.","DOI":"10.1145\/258305.258315"},{"key":"392095_CR2","first-page":"23","volume-title":"Advances in Computing Research","author":"P. R. Cappello","year":"1984","unstructured":"P. R. Cappello and K. Steiglitz. Unifying VLSI array design with linear transformations in space-time.In F. P. Preparata, ed., Advances in Computing Research, Vol. 2. pp. 23-65. JAI Press, Greenwich, 1984."},{"key":"392095_CR3","doi-asserted-by":"crossref","first-page":"1260","DOI":"10.1109\/PROC.1987.13878","volume":"75","author":"P. R. Cappelo","year":"1987","unstructured":"P. R. Cappelo and C.-W. Wu. Computer-aided design of VLSI FIR filters. Proceedings of the IEEE, 75: 1260-1271, 1987.","journal-title":"Proceedings of the IEEE"},{"key":"392095_CR4","first-page":"3","volume-title":"Parallel Architectures and Algorithms for Image Understanding","author":"C. Chakrabarti","year":"1991","unstructured":"C. Chakrabarti and J. J\u00e1J\u00e1. VLSI architectures for template matching and block matching. In V. K. P. Kumar, ed., Parallel Architectures and Algorithms for Image Understanding, pp. 3-27. Academic Press, Inc., San Diego, 1991."},{"issue":"12","key":"392095_CR5","doi-asserted-by":"crossref","first-page":"33","DOI":"10.1109\/2.642799","volume":"30","author":"T. M. Conte","year":"1997","unstructured":"T. M. Conte, P. K. Dubey, M. D. Jennings, R. B. Lee, A. Peleg, S. Rathnam, and M. Schlansker. Challenges to combining general-purpose and multimedia processors. Computer, 30(12): 33-37, 1997.","journal-title":"Computer"},{"key":"392095_CR6","first-page":"341","volume":"51","author":"Z. Galil","year":"1987","unstructured":"Z. Galil and R. Giancarle. Parallel string matching with k mismatches. TheoreticalComputing Science, 51: 341-348, 1987.","journal-title":"TheoreticalComputing Science"},{"issue":"4","key":"392095_CR7","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1109\/2.839324","volume":"33","author":"S. C. Goldstein","year":"2000","unstructured":"S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, and R. R. Taylor. PipeRench: A reconfigurable architecture and compiler. Computer, 33(4): 70-77, 2000.","journal-title":"Computer"},{"key":"392095_CR8","unstructured":"J. Hammes, R. Rinker, W. B\u00f6ohm, and W. Najjar. Cameron: high-level language compilation for reconfigurable systems. In PACT '99, 1999."},{"issue":"4","key":"392095_CR9","doi-asserted-by":"crossref","first-page":"50","DOI":"10.1109\/2.839321","volume":"33","author":"S. D. Haynes","year":"2000","unstructured":"S. D. Haynes, J. Stone, P. Y. Cheung, and W. Luk. Video image processing with Sonic architecture. Computer, 33(4): 50-57, April 2000.","journal-title":"Computer"},{"key":"392095_CR10","doi-asserted-by":"crossref","first-page":"71","DOI":"10.1007\/978-1-4615-3242-2_4","volume-title":"Applications-Driven Architecture Synthesis","author":"P. Held","year":"1993","unstructured":"P. Held and E. F. Deprettere. HiFi: from parallel algorithms to xed-size VLSI processor arrays. In F. Catthoor and L. Svensson, eds., Applications-Driven Architecture Synthesis, pp. 71-92. Kluwer Academic Publishers, Norwell, MA, 1993."},{"issue":"8","key":"392095_CR11","doi-asserted-by":"crossref","first-page":"27","DOI":"10.1109\/2.781631","volume":"32","author":"J. Hennessy","year":"1999","unstructured":"J. Hennessy. The future of system research. Computer, 32(8): 27-33, 1999.","journal-title":"Computer"},{"issue":"2","key":"392095_CR12","first-page":"69","volume":"2","author":"C. A. R. Hoare","year":"1994","unstructured":"C. A. R. Hoare and I. Page. Hardware and software: the closing gap. Transputer Communication, 2(2): 69-90, 1994.","journal-title":"Transputer Communication"},{"key":"392095_CR13","doi-asserted-by":"crossref","first-page":"331","DOI":"10.1016\/0167-9260(89)90024-2","volume":"8","author":"C.-W. Jen","year":"1989","unstructured":"C.-W. Jen and D.-M. Kwai. Multi-dimensional parallel computing structures for regular iterative algorithms. INTEGRATION, 8: 331-340, 1989.","journal-title":"INTEGRATION"},{"key":"392095_CR14","doi-asserted-by":"crossref","first-page":"37","DOI":"10.1109\/MC.1982.1653825","volume":"15","author":"H. T. Kung","year":"1982","unstructured":"H. T. Kung. Why systolic architectures? Computer,15: 37-46, 1982.","journal-title":"Computer"},{"key":"392095_CR15","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"397","DOI":"10.1007\/3-540-55599-4_101","volume-title":"Parallel Architectures and Languages Europe (PARLE '92)","author":"H. Le Verge","year":"1992","unstructured":"H. Le Verge. Reduction operators in ALPHA. In D. Etiemble and J.-C. Syre, eds., Parallel Architectures and Languages Europe (PARLE '92), Lecture Notes in Computer Science 605, pp. 397-410. Springer-Verlag, Berlin, 1992."},{"key":"392095_CR16","doi-asserted-by":"crossref","first-page":"173","DOI":"10.1007\/BF00925828","volume":"3","author":"H. Le Verge","year":"1991","unstructured":"H. Le Verge, C. Mauras, and P. Quinton. The ALPHA language and its use for the design of systolic arrays. Journalof VLSI Signal Processing, 3: 173-182, 1991.","journal-title":"Journalof VLSI Signal Processing"},{"key":"392095_CR17","doi-asserted-by":"crossref","first-page":"727","DOI":"10.1002\/spe.4380250703","volume":"25","author":"T. Lecroq","year":"1995","unstructured":"T. Lecroq. Experimental results on string matching with K mismatches. Software-Practice and Experience,25: 727-765, 1995.","journal-title":"Software-Practice and Experience"},{"key":"392095_CR18","volume-title":"Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes","author":"F. T. Leighton","year":"1992","unstructured":"F. T. Leighton. Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes. Morgan Kaufmann Publishers, San Mateo, CA, 1992."},{"key":"392095_CR19","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"398","DOI":"10.1007\/3-540-57208-2_28","volume-title":"CONCUR '93","author":"C. Lengauer","year":"1993","unstructured":"C. Lengauer. Loop parallelization in the polytope model. In E. Best, ed., CONCUR '93. Lecture Notes in Computer Science 715, pp. 398-416. Springer-Verlag, Berlin, 1993."},{"key":"392095_CR20","doi-asserted-by":"crossref","first-page":"368","DOI":"10.1016\/0743-7315(89)90026-9","volume":"7","author":"N. Ling","year":"1989","unstructured":"N. Ling and M. A. Bayoumi. Systematic algorithm mapping for multidimensional systolic arrays. Journal of Parallel and Distributed Computing, 7: 368-382, 1989.","journal-title":"Journal of Parallel and Distributed Computing"},{"key":"392095_CR21","doi-asserted-by":"crossref","first-page":"332","DOI":"10.1007\/978-1-4471-3544-9_18","volume-title":"Designing Correct Circuits","author":"W. Luk","year":"1991","unstructured":"W. Luk. Optimising designs by transposition. In G. Jones and M. Sheeran, eds., Designing Correct Circuits, pp. 332-354. Springer-Verlag, Berlin, 1991."},{"issue":"12","key":"392095_CR22","doi-asserted-by":"crossref","first-page":"38","DOI":"10.1109\/2.642810","volume":"30","author":"W. H. Mangione-Smith","year":"1997","unstructured":"W. H. Mangione-Smith, B. Hutchings, D. Andrews, A. Delton, C. Ebeling, R. Hartenstein, O. Mencer, J. Morris, K. Palem, V. K. Prasanna, and H. A. E. Spaanenburg. Seeking solution in configurable computing. Computer, 30(12): 38-43, 1997.","journal-title":"Computer"},{"key":"392095_CR23","volume-title":"An Introduction to Systolic Algorithm Design","author":"G. M. Megson","year":"1992","unstructured":"G. M. Megson. An Introduction to Systolic Algorithm Design. Clarendon Press, Oxford, UK, 1992."},{"key":"392095_CR24","first-page":"171","volume-title":"Parallel Computing","author":"G. M. Megson","year":"1985","unstructured":"G. M. Megson and D. J. Evans. Soft-systolic pipelined matrix algorithms. In M. Feilmeier, G. Joubert, and U. Schendel, eds., Parallel Computing 85, pp. 171-180. North-Holland, Amsterdam, 1985."},{"key":"392095_CR25","doi-asserted-by":"crossref","unstructured":"I. Page. Constructing hardware-software systems from a single description. Journalof VLSI Signal Processing, 87-107, December 1996.","DOI":"10.1007\/BF00936948"},{"key":"392095_CR26","first-page":"373","volume":"6","author":"T. P. Plaks","year":"1996","unstructured":"T. P. Plaks. Mesh of linear arrays for template matching. Special issue on special purpose architectures for realtime imaging. Real-Time Imaging Journal, 6: 373-382, 1996.","journal-title":"Special issue on special purpose architectures for realtime imaging. Real-Time Imaging Journal"},{"key":"392095_CR27","first-page":"321","volume":"13","author":"T. P. Plaks","year":"1999","unstructured":"T. P. Plaks. Efficient mapping reductions using isoplanes on the polytope model. Journal of Parallel Algorithms and Applications, 13: 321-343, 1999.","journal-title":"Journal of Parallel Algorithms and Applications"},{"key":"392095_CR28","unstructured":"T. P. Plaks. Piecewise Regular Arrays: Application-Specific Computations, Vol. 1 of Parallel Processing Series. Gordon and Breach Science Publishers, 1999."},{"key":"392095_CR29","first-page":"5","volume-title":"Proceedings of ICFEM 2000. Third IEEE International. configuring of algorithms in mapping into hardware 177 Conference on Formal Engineering Methods 2000","author":"T. P. Plaks","year":"2000","unstructured":"T. P. Plaks. Formal derivation of multilayered hardware\/software structures. In S. Liu, J. A. McDermid, and M. G. Hinchey, eds., Proceedings of ICFEM 2000. Third IEEE International. configuring of algorithms in mapping into hardware 177 Conference on Formal Engineering Methods 2000, York, England, UK. Sept. 4-6, 2000, pp. 5-13. IEEE Computer Society Press, Los Alamitos, CA, 2000."},{"key":"392095_CR30","doi-asserted-by":"crossref","unstructured":"T. P. Plaks. Parallel k-mismatching of strings using daughter-board structure. In J. Schewel, P. M. Athanas, C. H. Dick, and J. T. McHenry, eds., Reconfigurable Technology: FPGAs for Computing and Applications II,Proceedings of SPIE Vol. 4212, Nov. 5\u20138, 2000, Boston, MA, pp. 104-115, 2000.","DOI":"10.1117\/12.402514"},{"key":"392095_CR31","first-page":"208","volume-title":"Proceedings of the 11th Annual International Symposium on Computer Architecture","author":"P. Quinton","year":"1984","unstructured":"P. Quinton. Automatic synthesis of systolic arrays from uniform recurrent equations. In Proceedings of the 11th Annual International Symposium on Computer Architecture, pp. 208-214. IEEE Computer Society Press, Los Alamitos, CA, 1984."},{"key":"392095_CR32","volume-title":"Systolic Algorithms and Architectures","author":"P. Quinton","year":"1991","unstructured":"P. Quinton and Y. Robert. Systolic Algorithms and Architectures. Prentice Hall, Masson, UK, 1991."},{"key":"392095_CR33","doi-asserted-by":"crossref","first-page":"88","DOI":"10.1007\/BF01558666","volume":"3","author":"S. V. Rajopadhye","year":"1989","unstructured":"S. V. Rajopadhye. Synthesizing systolic arrays with control signals from recurrence equations. Distributed Computing, 3: 88-105, 1989.","journal-title":"Distributed Computing"},{"key":"392095_CR34","doi-asserted-by":"crossref","first-page":"259","DOI":"10.1109\/5.4402","volume":"76","author":"S. Rao","year":"1988","unstructured":"S. Rao and T. Kailath. Regular iterative algorithms and their implementations on processor arrays. Proceedings of IEEE, 76: 259-282, 1988.","journal-title":"Proceedings of IEEE"},{"key":"392095_CR35","first-page":"297","volume":"14","author":"J. Teich","year":"1993","unstructured":"J. Teich and L. Thiele. Partitioning of processor arrays: a piecewise regular approach. INTEGERATION,14: 297-332, 1993.","journal-title":"INTEGERATION"},{"key":"392095_CR36","volume-title":"DigitalCircuit Design","author":"N. Writh","year":"1995","unstructured":"N. Writh. DigitalCircuit Design. Springer-Verlag, New York, 1995."},{"issue":"6","key":"392095_CR37","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1109\/2.683004","volume":"31","author":"N. Wirth","year":"1998","unstructured":"N. Wirth. Hardware compilation: Translating programs into circuits. Computer, 31(6): 25-31, 1998.","journal-title":"Computer"},{"key":"392095_CR38","doi-asserted-by":"crossref","first-page":"135","DOI":"10.1007\/BF00924523","volume":"12","author":"J.-W. Yeh","year":"1996","unstructured":"J.-W. Yeh, W.-J. Cheng,and C.-W. Jen. VASS-a VLSI array system synthesizer. Journal of VLSI Signal Processing,12: 135-158, 1996.","journal-title":"Journal of VLSI Signal Processing"}],"container-title":["The Journal of Supercomputing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1013679420784.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1023\/A:1013679420784\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1013679420784.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,8]],"date-time":"2025-08-08T05:28:05Z","timestamp":1754630885000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1023\/A:1013679420784"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,2]]},"references-count":38,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2002,2]]}},"alternative-id":["392095"],"URL":"https:\/\/doi.org\/10.1023\/a:1013679420784","relation":{},"ISSN":["0920-8542","1573-0484"],"issn-type":[{"type":"print","value":"0920-8542"},{"type":"electronic","value":"1573-0484"}],"subject":[],"published":{"date-parts":[[2002,2]]}}}