{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:40:06Z","timestamp":1749206406102,"version":"3.41.0"},"reference-count":27,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2002,4,1]],"date-time":"2002-04-01T00:00:00Z","timestamp":1017619200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2002,4,1]],"date-time":"2002-04-01T00:00:00Z","timestamp":1017619200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Electronic Testing"],"published-print":{"date-parts":[[2002,4]]},"DOI":"10.1023\/a:1014968930415","type":"journal-article","created":{"date-parts":[[2002,12,28]],"date-time":"2002-12-28T21:55:50Z","timestamp":1041112550000},"page":"231-240","source":"Crossref","is-referenced-by-count":5,"title":["Reusing Scan Chains for Test Pattern Decompression"],"prefix":"10.1007","volume":"18","author":[{"given":"Rainer","family":"Dorsch","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hans-Joachim","family":"Wunderlich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"6","key":"397093_CR1","doi-asserted-by":"crossref","first-page":"806","DOI":"10.1109\/12.391181","volume":"44","author":"S. Boubezari","year":"1995","unstructured":"S. Boubezari and B. Kami\u0148ska, \u201cA Deterministic Built-in Self-Test generator based on Cellular Automata Structures,\u201d IEEE Transactions on Computers, vol. 44, no.6, pp. 806\u2013816, 1995.","journal-title":"IEEE Transactions on Computers"},{"key":"397093_CR2","first-page":"1229","volume-title":"Proceedings of the International Symposium on Circuits and Systems (ISCAS)","author":"F. Brglez","year":"1989","unstructured":"F. Brglez, D. Bryan, and K. Kozminski, \u201cCombinatorial Profiles of Sequential Benchmark Circuits,\u201d in Proceedings of the International Symposium on Circuits and Systems (ISCAS), 1989, New York: IEEE, pp. 1229\u20131234."},{"key":"397093_CR3","doi-asserted-by":"crossref","unstructured":"S. Cataldo, S. Chiusano, P. Prinetto, and H.-J. Wunderlich, \u201cOptimal Hardware Pattern Generation for Functional BIST,\u201d in Proceedings of the Design Automation and Test in Europe (DATE), 2000.","DOI":"10.1145\/343647.343784"},{"issue":"8","key":"397093_CR4","doi-asserted-by":"crossref","first-page":"916","DOI":"10.1109\/43.644618","volume":"16","author":"K. Chakrabarty","year":"1997","unstructured":"K. Chakrabarty and J.P. Hayes, \u201cOn the Quality of Accumulator-Based Compaction of Test Responses,\u201d IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 8, pp. 916\u2013922, Aug. 1997.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"397093_CR5","doi-asserted-by":"crossref","unstructured":"A. Chandra and K. Chakrabarty, \u201cSystem-on-a-Chip Test Data Compression and Decompression Architectures Based on Golomb Codes,\u201d IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20, March 2001.","DOI":"10.1109\/43.913754"},{"issue":"12","key":"397093_CR6","doi-asserted-by":"crossref","first-page":"1086","DOI":"10.1109\/TC.1986.1676718","volume":"C-35","author":"C.L. Chen","year":"1986","unstructured":"C.L. Chen, \u201cLinear Dependencies in Linear Feedback Shift Registers,\u201d IEEE Transactions on Computers, vol. C-35, no. 12, pp. 1086\u20131088, Dec. 1986.","journal-title":"IEEE Transactions on Computers"},{"key":"397093_CR7","first-page":"644","volume-title":"Proceedings of the IEEE International Test Conference (ITC)","author":"S. Chiusano","year":"2000","unstructured":"S. Chiusano, P. Prinetto, and H.-J. Wunderlich, \u201cNon-Intrusive BIST for Systems-on-a-Chip.\u201d in Proceedings of the IEEE International Test Conference (ITC), Atlantic City, NJ, 2000, New York: IEEE, pp. 644\u2013651."},{"key":"397093_CR8","unstructured":"W. Daehn and J. Mucha, \u201cHardware Test Pattern Generators for Built-in Test,\u201d in Proceedings of the IEEE International Test Conference (ITC), Cherry Hill, NJ, 1991, pp. 110\u2013113."},{"key":"397093_CR9","first-page":"115","volume-title":"Proceedings of the IEEE International Test Conference (ITC)","author":"D. Das","year":"2000","unstructured":"D. Das and N.A. Touba, \u201cReducing Test Data Volume Using External\/LBIST Hybrid Test Patterns,\u201d in Proceedings of the IEEE International Test Conference (ITC), Atlanta, NJ, 2000, New York: IEEE, pp. 115\u2013122."},{"key":"397093_CR10","doi-asserted-by":"crossref","unstructured":"R. Dorsch and H.-J. Wunderlich, \u201cAccumulator Based Deterministic BIST,\u201d In Proceedings of the IEEE International Test Conference (ITC), 1998, pp. 412\u2013421.","DOI":"10.1109\/TEST.1998.743181"},{"key":"397093_CR11","doi-asserted-by":"crossref","unstructured":"I. Ghosh, S. Dey, and N.K. Jha, \u201cA Fast and Low Cost Testing Technique for Core-Based System-on-Chip,\u201d in Design Automation Conference, June 1998, pp. 542\u2013547.","DOI":"10.1145\/277044.277190"},{"key":"397093_CR12","unstructured":"P. Goel and B.C. Rosales, \u201cTest Generation and Dynamic Compaction of Tests,\u201d in Digest of Papers Test Conference, 1979, pp. 189\u2013192."},{"key":"397093_CR13","unstructured":"X. Gu, S.S. Chung, F. Tsang, J.A. Tofte, and H. Rahmanian, \u201cA Fast Timing Closure Technique for Industrial Use of Logic BIST,\u201d Presentation at the European TestWorkshop (ETW), May 2001."},{"key":"397093_CR14","doi-asserted-by":"crossref","unstructured":"I. Hamzaoglu and J.H. Patel, \u201cTest Set Compaction Algorithms for Combinational Circuits,\u201d in Proceedings of the International Conference on CAD (ICCAD), Nov. 1998.","DOI":"10.1145\/288548.288615"},{"issue":"1","key":"397093_CR15","doi-asserted-by":"crossref","first-page":"127","DOI":"10.1023\/A:1008294125692","volume":"12","author":"S. Hellebrand","year":"1998","unstructured":"S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, \u201cMixed-Mode BIST Using Embedded Processors,\u201d Journal of Electronic Testing Theory and Applications, vol. 12, no. 1\/2, pp. 127\u2013138, 1998.","journal-title":"Journal of Electronic Testing Theory and Applications"},{"key":"397093_CR16","doi-asserted-by":"crossref","unstructured":"V. Immaneni and S. Raman, \u201cDirect Access Test Scheme-Design of Block and Core Cells for Embedded ASICs,\u201d in Proceedings of the IEEE International Test Conference (ITC), Oct. 1990, pp. 488\u2013492.","DOI":"10.1109\/TEST.1990.114058"},{"key":"397093_CR17","unstructured":"B. Koenemann, \u201cLFSR-Coded Test Patterns for Scan Design,\u201d in Proceedings of the European Test Conference (ETC), M\u00a8unchen, 1991, pp. 237\u2013242."},{"key":"397093_CR18","first-page":"616","volume-title":"Proceedings of the IEEE International Test Conference (ITC)","author":"E.J. Marinissen","year":"1999","unstructured":"E.J. Marinissen, Y. Zorian, R. Kapur, T. Taylor, and L. Whetsel, \u201cTowards a Standard for Embedded Core Test: An Example,\u201d in Proceedings of the IEEE International Test Conference (ITC), 1999, New York: IEEE, pp. 616\u2013627."},{"issue":"1","key":"397093_CR19","doi-asserted-by":"crossref","first-page":"129","DOI":"10.1023\/A:1008340519743","volume":"15","author":"M. Nourani","year":"1999","unstructured":"M. Nourani and C. Papachristou, \u201cStructural Fault Testing of Embedded Cores Using Pipelining,\u201d Journal of Electronic Testing Theory and Applications, vol. 15, no. 1\/2, pp. 129\u2013144, Aug.\/Oct. 1999.","journal-title":"Journal of Electronic Testing Theory and Applications"},{"key":"397093_CR20","unstructured":"P1500 Scalable Architecture Task Force, \u201cPreliminary Outline of IEEE P1500 Scalable Architecture for Testing Embeddeb Cores,\u201d in VLSI Test Symposium, May 1999."},{"issue":"6","key":"397093_CR21","doi-asserted-by":"crossref","first-page":"643","DOI":"10.1109\/12.277285","volume":"42","author":"J. Rajski","year":"1993","unstructured":"J. Rajski and J. Tyszer, \u201cAccumulator-Based Compaction of Test Responses,\u201d IEEE Transactions on Computers, vol. 42, no. 6, pp. 643\u2013650, June 1993.","journal-title":"IEEE Transactions on Computers"},{"issue":"11","key":"397093_CR22","doi-asserted-by":"crossref","first-page":"1188","DOI":"10.1109\/12.736428","volume":"47","author":"J. Rajski","year":"1998","unstructured":"J. Rajski, J. Tyszer, and N. Zacharia, \u201cTest Data Decompression for Multiple Scan Designs with Boundary Scan,\u201d IEEE Transactions on Computers, vol. 47, no. 11, pp. 1188\u20131200, Nov. 1998.","journal-title":"IEEE Transactions on Computers"},{"key":"397093_CR23","volume-title":"The International Technology Roadmap for Semiconductors (ITRS)","author":"Semiconductor Industry Association","year":"1999","unstructured":"Semiconductor Industry Association, The International Technology Roadmap for Semiconductors (ITRS), International SEMATECH, Austin, TX, 1999."},{"key":"397093_CR24","doi-asserted-by":"crossref","first-page":"380","DOI":"10.1109\/VTEST.1996.510882","volume-title":"Proceedings of the VLSI Test Symposium (VTS)","author":"A.P. Str\u00d6le","year":"1996","unstructured":"A.P. Str\u00d6le, \u201cTest Response Compaction using Arithmetic Functions,\u201d in Proceedings of the VLSI Test Symposium (VTS), 1996, New York: IEEE, pp. 380\u2013386."},{"key":"397093_CR25","doi-asserted-by":"crossref","unstructured":"P. Varma and S. Bhatia, \u201cAStructured Test Re-Use Methodology for Core Based System-Chips,\u201d in Proceedings of the IEEE International Test Conference (ITC),Washington, DC, Oct. 1998, pp. 294\u2013302.","DOI":"10.1109\/TEST.1998.743167"},{"issue":"7","key":"397093_CR26","doi-asserted-by":"crossref","first-page":"54","DOI":"10.1109\/6.774966","volume":"36","author":"Y. Zorian","year":"1999","unstructured":"Y. Zorian, \u201cTesting the Monster Chip,\u201d IEEE Spectrum, vol. 36, no. 7, pp. 54\u201360, July 1999.","journal-title":"IEEE Spectrum"},{"key":"397093_CR27","first-page":"130","volume-title":"Proceedings of the IEEE International Test Conference (ITC)","author":"Y. Zorian","year":"1998","unstructured":"Y. Zorian, E. Marinissen, and S. Dey, \u201cTesting Embedded-Core-Based System Chips,\u201d in Proceedings of the IEEE International Test Conference (ITC), 1998, New York: IEEE, pp. 130\u2013143."}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1014968930415.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1023\/A:1014968930415\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1014968930415.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:08:49Z","timestamp":1749204529000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1023\/A:1014968930415"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,4]]},"references-count":27,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2002,4]]}},"alternative-id":["397093"],"URL":"https:\/\/doi.org\/10.1023\/a:1014968930415","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2002,4]]}}}