{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,17]],"date-time":"2026-08-17T21:17:24Z","timestamp":1787001444572,"version":"build-2736575974"},"reference-count":20,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2002,6,1]],"date-time":"2002-06-01T00:00:00Z","timestamp":1022889600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2002,6,1]],"date-time":"2002-06-01T00:00:00Z","timestamp":1022889600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology"],"published-print":{"date-parts":[[2002,6]]},"DOI":"10.1023\/a:1015333103608","type":"journal-article","created":{"date-parts":[[2002,12,28]],"date-time":"2002-12-28T18:08:17Z","timestamp":1041098897000},"page":"77-89","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":42,"title":["A 16-Bit by 16-Bit MAC Design Using Fast 5:3 Compressor Cells"],"prefix":"10.1007","volume":"31","author":[{"given":"Ohsang","family":"Kwon","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kevin","family":"Nowka","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"suffix":"Jr.","given":"Earl E.","family":"Swartzlander","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2002,7,1]]},"reference":[{"key":"406086_CR1","doi-asserted-by":"publisher","first-page":"14","DOI":"10.1109\/PGEC.1964.263830","volume":"EC-13","author":"C.S. Wallace","year":"1964","unstructured":"C.S. Wallace, \u201cA Suggestion For a Fast Multiplier,\u201d IEEE Trans. on Electronic Computers, vol. EC-13, 1964, pp. 14-17.","journal-title":"IEEE Trans. on Electronic Computers"},{"key":"406086_CR2","first-page":"349","volume":"34","author":"L. Dadda","year":"1965","unstructured":"L. Dadda, \u201cSome Schemes for Parallel Multiplier,\u201d Alta Freq., vol. 34, 1965, pp. 349-356.","journal-title":"Alta Freq."},{"key":"406086_CR3","doi-asserted-by":"publisher","first-page":"67","DOI":"10.1109\/JRPROC.1961.287779","volume":"49","author":"O.L. MacSoley","year":"1961","unstructured":"O.L. MacSoley, \u201cHigh Speed Arithmetic in Binary Computers,\u201d Proc. IRE, vol. 49, 1961, pp. 67-91.","journal-title":"Proc. IRE"},{"key":"406086_CR4","doi-asserted-by":"publisher","first-page":"1006","DOI":"10.1109\/12.57039","volume":"39","author":"H. Sam","year":"1990","unstructured":"H. Sam and A. Gupta, \u201cA Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementation,\u201d IEEE Trans. on Computers, vol. 39, 1990, pp. 1006-1015.","journal-title":"IEEE Trans. on Computers"},{"key":"406086_CR5","doi-asserted-by":"publisher","first-page":"172","DOI":"10.1109\/12.16494","volume":"38","author":"S. Vassiliadis","year":"1989","unstructured":"S. Vassiliadis, E.M. Swartz, and D.J. Hanrahan, \u201cA General Proof for Overlapped Multiple-Bit Scanning Multiplications,\u201d IEEE Trans. on Computers, vol. 38, 1989, pp. 172-183.","journal-title":"IEEE Trans. on Computers"},{"key":"406086_CR6","doi-asserted-by":"publisher","first-page":"1184","DOI":"10.1109\/4.84935","volume":"26","author":"P.J. Song","year":"1991","unstructured":"P.J. Song and G.D. Micheli, \u201cCircuit and Architecture Tradeoffs for High-Speed Multiplication,\u201d IEEE Journal of Solid-State Circuits, vol. 26, 1991, pp. 1184-1198.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"406086_CR7","doi-asserted-by":"publisher","first-page":"294","DOI":"10.1109\/12.485568","volume":"45","author":"V.G. Oklobdzija","year":"1996","unstructured":"V.G. Oklobdzija, D. Villeger, and S.S. Liu, \u201cA Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach,\u201d IEEE Trans. on Computers, vol. 45, 1996, pp. 294-305.","journal-title":"IEEE Trans. on Computers"},{"key":"406086_CR8","doi-asserted-by":"publisher","first-page":"388","DOI":"10.1109\/4.52161","volume":"25","author":"K. Yano","year":"1990","unstructured":"K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A. Shimizu, \u201cA 3.8-ns CMOS 16 \u00d7 16-b Multiplier Using Complementary Pass-Transistor Logic,\u201d IEEE Journal of Solid-State Circuits, vol. 25, 1990, pp. 388-395.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"406086_CR9","doi-asserted-by":"publisher","first-page":"804","DOI":"10.1109\/4.509866","volume":"31","author":"A. Parameswar","year":"1994","unstructured":"A. Parameswar, H. Hara, and T. Sakurai, \u201cA Swing Restored Pass-Transistor Logic-Based Multiply and Accumulator Circuit for Multimedia Applications,\u201d IEEE Journal of Solid-State Circuits, vol. 31, 1994, pp. 804-809.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"406086_CR10","doi-asserted-by":"publisher","first-page":"52","DOI":"10.1109\/4.553178","volume":"32","author":"M. Izumikawa","year":"1997","unstructured":"M. Izumikawa, H. Igura, K. Furuta, H. Ito, H. Wakabayashi, K. Nakajima, T. Mogami, T. Horiuchi, and M. Yamashina, \u201cA 0.25-\u03bcm CMOS 0.9-V 100-MHz DSP Core,\u201d IEEE Journal of Solid-State Circuits, vol. 32, 1997, pp. 52-61.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"406086_CR11","doi-asserted-by":"publisher","first-page":"251","DOI":"10.1109\/4.364439","volume":"30","author":"N. Ohkubo","year":"1993","unstructured":"N. Ohkubo, M. Suzuki, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, and Y. Nakagome, \u201cA 4.4 ns CMOS 54 \u00d7 54-b Multiplier Using Pass-Transistor Multiplexer,\u201d IEEE Journal of Solid-State Circuits, vol. 30, 1993, pp. 251-257.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"406086_CR12","doi-asserted-by":"publisher","first-page":"1395","DOI":"10.1109\/4.792613","volume":"34","author":"C.F. Law","year":"1999","unstructured":"C.F. Law, S.S. Rofail, and K.S. Yeo, \u201cA Low-Power 16 \u00d7 16-b Parallel Multiplier Utilizing Pass-Transistor Logic,\u201d IEEE Journal of Solid-State Circuits, vol. 34, 1999, pp. 1395-1399.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"406086_CR13","unstructured":"O. Kwon, K. Nowka, and E. Swartzlander, Jr., \u201cA 16-bit \u00d7 16-bit MAC Design Using Fast 5:2 Compressors,\u201d in International Conference on Application-Specific Systems, Architectures, and Processors, 2000, pp. 235-243."},{"key":"406086_CR14","doi-asserted-by":"publisher","first-page":"1045","DOI":"10.1109\/T-C.1973.223648","volume":"C-22","author":"C.R. Baugh","year":"1973","unstructured":"C.R. Baugh and B.A. Wooley, \u201cA Two's Complement Parallel Array Multiplication Algorithm,\u201d IEEE Trans. Computers, vol. C-22, 1973, pp. 1045-1047.","journal-title":"IEEE Trans. Computers"},{"key":"406086_CR15","doi-asserted-by":"publisher","first-page":"1181","DOI":"10.1109\/12.102823","volume":"40","author":"S. Vassiliadis","year":"1991","unstructured":"S. Vassiliadis, E.M. Swartz, and B.M. Sung, \u201cHard-Wired Multipliers with Encoded Partial Products,\u201d IEEE Trans. on Computers, vol. 40, 1991, pp. 1181-1197.","journal-title":"IEEE Trans. on Computers"},{"key":"406086_CR16","doi-asserted-by":"publisher","first-page":"1676","DOI":"10.1109\/4.641687","volume":"32","author":"G. Goto","year":"1997","unstructured":"G. Goto, A. Inoue, R. Ohe, S. Kashiwakura, S. Mitarai, T. Tsuru, and T. Izawa, \u201cA 4.1-ns Compact 54 \u00d7 54-b Multiplier Utilizing Sign-Select Booth Encoders,\u201d IEEE Journal of Solid-State Circuits, vol. 32, 1997, pp. 1676-1682.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"406086_CR17","doi-asserted-by":"crossref","unstructured":"L. Su, R. Schulz, J. Adkisson, K. Beyer, G. Biery, W. Cote, E. Crabbe, D. Edelstein, J. Ellis-Monaghan, E. Eld, D. Foster, R. Gehres, R. Goldblatt, N. Greco, C. Guenther, J. Heidenreich, J. Herman, D. Kiesling, L. Lin, S.-H. Lo, J. McKenna, C. Megivern, H. Ng, J. Oberschmidt, A. Ray, N. Rohrer, K. Tallman, T. Wagner, and B. Davari, \u201cA High-Performance Sub-0.25 \u03bcm CMOS Technology with Multiple Thresholds and Copper Interconnects,\u201d in 1998 Symposium on VLSI Technology Digest of Technical Papers, 1998, pp. 18-19.","DOI":"10.1109\/VLSIT.1998.689182"},{"key":"406086_CR18","volume-title":"Principles of CMOS VLSI Design: A Systems Perspective","author":"N. H. Weste","year":"1993","unstructured":"Neil H.E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd ed., Santa Clara, CA: Addison-Wesley Publishing Company, 1993.","edition":"2nd ed."},{"key":"406086_CR19","doi-asserted-by":"crossref","unstructured":"Kevin J. Nowka and Tibi Galambos, \u201cCircuit Design Techniques for a Gigahertz Integer Microprocessor,\u201d in International Conference on Computer Design, 1998, pp. 11-16.","DOI":"10.1109\/ICCD.1998.727017"},{"key":"406086_CR20","doi-asserted-by":"publisher","first-page":"1600","DOI":"10.1109\/4.726542","volume":"33","author":"J. Silberman","year":"1998","unstructured":"J. Silberman, N. Aoki, D. Boerstler, J. Burns, S. Dhong, A. Essbaum, U. Ghoshal, D. Heidel, P. Hofstee, K. Lee, D. Meltzer, H. Ngo, K. Nowka, S. Posluszny, O. Takahashi, I. Vo, and B. Zoric, \u201cA 1.0 GHz Single-Issue 64-Bit PowerPC Integer Processor,\u201d IEEE Journal of Solid-State Circuits, vol. 33, 1998, pp. 1600-1608.","journal-title":"IEEE Journal of Solid-State Circuits"}],"container-title":["Journal of VLSI signal processing systems for signal, image and video technology"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1015333103608.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1023\/A:1015333103608\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1015333103608.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,11]],"date-time":"2025-08-11T09:39:15Z","timestamp":1754905155000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1023\/A:1015333103608"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,6]]},"references-count":20,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2002,6]]}},"alternative-id":["406086"],"URL":"https:\/\/doi.org\/10.1023\/a:1015333103608","relation":{},"ISSN":["0922-5773"],"issn-type":[{"value":"0922-5773","type":"print"}],"subject":[],"published":{"date-parts":[[2002,6]]},"assertion":[{"value":"1 July 2002","order":1,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}