{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,7]],"date-time":"2025-06-07T04:03:54Z","timestamp":1749269034299,"version":"3.41.0"},"reference-count":29,"publisher":"Springer Science and Business Media LLC","issue":"4-5","license":[{"start":{"date-parts":[[2002,8,1]],"date-time":"2002-08-01T00:00:00Z","timestamp":1028160000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2002,8,1]],"date-time":"2002-08-01T00:00:00Z","timestamp":1028160000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Electronic Testing"],"published-print":{"date-parts":[[2002,8]]},"DOI":"10.1023\/a:1016597624753","type":"journal-article","created":{"date-parts":[[2002,12,29]],"date-time":"2002-12-29T03:32:49Z","timestamp":1041132769000},"page":"455-473","source":"Crossref","is-referenced-by-count":10,"title":["CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing"],"prefix":"10.1007","volume":"18","author":[{"given":"Mounir","family":"Benabdenbi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Walid","family":"Maroufi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Meryem","family":"Marzouki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"5090059_CR1","doi-asserted-by":"crossref","unstructured":"M. Benabdenbi, W. Maroufi, and M. Marzouki, \u201cCas-Bus: A Scalable and ReconfigurableTest Acces Mechanism for Systems on a Chip, \u201d in IEEE Design Automation and Test in Europe (DATE), Paris, France, March 2000, pp. 141\u2013145.","DOI":"10.1145\/343647.343720"},{"key":"5090059_CR2","doi-asserted-by":"crossref","unstructured":"M. Benabdenbi, W. Maroufi, and M. Marzouki, \u201cTesting Taped Cores and Wrapped Cores with the Same Test Access Mechanism, \u201d in IEEE Design Automation and Test in Europe (DATE), Munich, Germany, March 2001, pp. 150\u2013155.","DOI":"10.1109\/DATE.2001.915016"},{"key":"5090059_CR3","doi-asserted-by":"crossref","unstructured":"D. Bhattacharya, \u201cHierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit, \u201d in IEEE VLSI Test Symposium (VTS), Dana Point (CA), USA, April 1998, pp. 8\u201314.","DOI":"10.1109\/VTEST.1998.670842"},{"key":"5090059_CR4","doi-asserted-by":"crossref","unstructured":"K. Chakrabarty, \u201cDesign of System on a Chip Test Access Architectures Under Place-and-Route and Power Constraints, \u201d in IEEE\/ACMDesign Automation Conference (DAC), Los Angeles (CA), USA, June 2000, pp. 432\u2013437.","DOI":"10.1145\/337292.337531"},{"issue":"1","key":"5090059_CR5","doi-asserted-by":"crossref","first-page":"26","DOI":"10.1145\/371254.371258","volume":"6","author":"K. Chakrabarty","year":"2001","unstructured":"K. Chakrabarty, \u201cOptimal Test Access Architectures for System on a Chip, \u201d ACM Trans. Design Automation of Electronic Systems, vol. 6, no. 1, pp. 26\u201349, Jan. 2001.","journal-title":"ACM Trans. Design Automation of Electronic Systems"},{"key":"5090059_CR6","unstructured":"B. Dervisoglu and J. Swamy, \u201cANovel Approach for Designing a Hierarchical Test Access Controller for Embedded Core Designs in an SoC Environment, \u201d in 4th IEEE InternationalWorkshop on Testing Embedded Core-Based System-Chips (TECS), Montreal (QC), Canada, May 2000, pp. 1.4.1\u20131.4.7."},{"key":"5090059_CR7","unstructured":"C. Feige and C. Wouters, \u201cIntegration of Structural Test Methods into an Architecture Specific Core-Test Approach, \u201d in 2nd IEEE InternationalWorkshop on Testing Embedded Core-Based System-Chips (TECS), Washington (DC), USA, Oct. 1998, pp. 5.2.1\u20135.2.8."},{"key":"5090059_CR8","unstructured":"S.K. Goel and E.J. Marinissen, \u201cTAM Architectures and their Implication on Test Application Time, \u201d in IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), Marina del Rey (CA), USA, May 2001, pp. 3.3.1\u20133.3.10."},{"key":"5090059_CR9","unstructured":"IEEE P1500 Standard for Embedded Core Test Web Site, http:\/\/grouper.ieee.org\/groups\/1500. Public Informations."},{"key":"5090059_CR10","doi-asserted-by":"crossref","unstructured":"V. Iyengar, K. Chakrabarty, and E.J. Marinissen, \u201cTest Wrapper and Test Acces Mechanism Co-Optimization for System on a Chip, \u201d in IEEE International Test Conference (ITC), Baltimore, MD, USA, Oct. 2001, pp. 1023\u20131032.","DOI":"10.1109\/TEST.2001.966728"},{"key":"5090059_CR11","unstructured":"A. Jas, J. Ghosh-Dastidar, and N.A. Touba, \u201cScan Vector Compression\/Decompression Using Statistical Coding, \u201d in 17th IEEE VLSI Test Symposium (VTS), San Diego (CA), USA, April 1999."},{"key":"5090059_CR12","doi-asserted-by":"crossref","unstructured":"A. Jas and N.A Touba, \u201cTestVector DecompressionVia Cyclical Scan Chains and its Application toTesting Core-Based Designs, \u201d in IEEE International Test Conference (ITC),Washington (DC), USA, 1998, pp. 458\u2013464.","DOI":"10.1109\/TEST.1998.743186"},{"key":"5090059_CR13","doi-asserted-by":"crossref","unstructured":"E. Larsson and Z. Peng, \u201cAn Integrated System on a Chip Test Framework, \u201d in IEEE Design Automation and Test in Europe Conference (DATE), Munich, Germany, March 2001, pp. 138\u2013144.","DOI":"10.1109\/DATE.2001.915014"},{"issue":"3","key":"5090059_CR14","doi-asserted-by":"crossref","first-page":"261","DOI":"10.1145\/45072.45074","volume":"19","author":"D.A. Lelewer","year":"1987","unstructured":"D.A. Lelewer and D.S. Hirschberg, \u201cData Compression, \u201d ACM Computing Surveys (CSUR), vol. 19, no. 3, pp. 261\u2013296, Sept. 1987.","journal-title":"ACM Computing Surveys (CSUR)"},{"key":"5090059_CR15","unstructured":"LIP6-ASIM, Alliance CAD System. http:\/\/www-asim.lip6. fr\/alliance\/. University Paris 6-France."},{"key":"5090059_CR16","unstructured":"E.J. Marinissen, R. Arendsen, G. Bos, H. Dingemanse, M. Lousberg, and C. Wouters, \u201cA Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores, \u201d in IEEE International Test Conference (ITC), Washington (DC), USA, Oct. 1998."},{"key":"5090059_CR17","doi-asserted-by":"crossref","unstructured":"E.J. Marinissen and M. Lousberg, \u201cThe Role of Test Protocol in Testing Embedded Core-Based System Ics, \u201d in IEEE European TestWorkshop (ETW), Constance, Germany, May 1999, pp. 70\u201375.","DOI":"10.1109\/ETW.1999.804248"},{"key":"5090059_CR18","unstructured":"E.J. Marinissen, Y. Zorian, R. Kapur, T. Taylor, and L. Whetsel, \u201cTowards a Standard for Embedded Core Test: An Example, \u201d in IEEE International Test Conference (ITC), Atlantic City (NJ), USA, Sept. 1999."},{"key":"5090059_CR19","doi-asserted-by":"crossref","unstructured":"W. Maroufi, M. Benabdenbi, and M. Marzouki, \u201cSolving the I\/O Bandwith Problem in System on a Chip Testing, \u201d in XIII Symposium on Integrated Circuits and System Design (SBCCI), Manaus (AM), Brazil, Sept. 2000, pp. 9\u201314.","DOI":"10.1109\/SBCCI.2000.876001"},{"key":"5090059_CR20","unstructured":"W. Maroufi, M. Benabdenbi, and M. Marzouki, \u201cControlling the CAS-BUS TAM with IEEE 1149.1 TAP: A Solution for Systems on a Chip Testing, \u201d in 4th IEEE InternationalWorkshop on Testing Embedded Core-Based System-Chips (TECS), Montreal (QC), Canada, May 2000, pp. 4.5.1\u20134.5.6."},{"key":"5090059_CR21","unstructured":"Synopsys, Synopsys Design Compiler Family. http:\/\/www. synopsys.com\/products\/logic\/logic.html. Synopsys, Inc."},{"key":"5090059_CR22","doi-asserted-by":"crossref","unstructured":"J. van Beers and H. van Herten, \u201cTest Features of a Core-Based Co-Processor Array for Video Applications, \u201d in IEEE International Test Conference (ITC), Atlantic City (NJ), USA, Sept. 1999, pp. 638\u2013647.","DOI":"10.1109\/TEST.1999.805788"},{"key":"5090059_CR23","unstructured":"P. Varma and S. Bhatia, \u201cA Structured Test Reuse Methodology for Core-Based System Chips, \u201d in IEEE International Test Conference (ITC), Washington (DC), USA, Oct. 1998."},{"key":"5090059_CR24","unstructured":"F. Wajsb\u00a8urt, J.L. Desbarbieux, C. Spasevski, S. Penain, and A. Greiner, \u201cAn Integrated PCI Component for IEEE 1355, \u201d in European Multimedia Microprocessor Systems and Electronic Commerce Conference and Exhibition, Florence, Italy, Nov. 1997."},{"key":"5090059_CR25","doi-asserted-by":"crossref","unstructured":"L. Whetsel, \u201cAn IEEE 1149.1 Based Test Acces Architecture for ics with Embedded Cores, \u201d in IEEE International Test Conference (ITC), Washington (DC), USA, Nov. 1997, pp. 69\u201378.","DOI":"10.1109\/TEST.1997.639596"},{"key":"5090059_CR26","doi-asserted-by":"crossref","unstructured":"L. Whetsel, \u201cAddressable Test Ports an Approach to Testing Embedded Cores, \u201d in IEEE International Test Conference (ITC), Atlantic City (NJ), USA, Sept. 1999, pp. 1055\u20131064.","DOI":"10.1109\/TEST.1999.805839"},{"key":"5090059_CR27","unstructured":"L. Whetsel and M. Ricchetti, \u201cTapping into IEEE P1500 Domains, \u201d in 5th IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), Los Angeles (CA), USA, May 2001."},{"issue":"6","key":"5090059_CR28","doi-asserted-by":"crossref","first-page":"520","DOI":"10.1145\/214762.214771","volume":"30","author":"I.H. Witten","year":"1987","unstructured":"I.H. Witten, R.M. Neal, and J.G. Cleary, \u201cArithmetic Coding for Data Compression, \u201d Communications of the ACM, vol. 30, no. 6, pp. 520\u2013540, June 1987.","journal-title":"Communications of the ACM"},{"key":"5090059_CR29","doi-asserted-by":"crossref","unstructured":"Y. Zorian, \u201c Testing the Monster Chip, \u201d in IEEE Spectrum, July 1999, pp. 54\u201360.","DOI":"10.1109\/6.774966"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1016597624753.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1023\/A:1016597624753\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1016597624753.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:03:47Z","timestamp":1749204227000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1023\/A:1016597624753"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,8]]},"references-count":29,"journal-issue":{"issue":"4-5","published-print":{"date-parts":[[2002,8]]}},"alternative-id":["5090059"],"URL":"https:\/\/doi.org\/10.1023\/a:1016597624753","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2002,8]]}}}