{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,15]],"date-time":"2025-07-15T00:02:05Z","timestamp":1752537725712,"version":"3.41.2"},"reference-count":19,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2002,11,1]],"date-time":"2002-11-01T00:00:00Z","timestamp":1036108800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2002,11,1]],"date-time":"2002-11-01T00:00:00Z","timestamp":1036108800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Design Automation for Embedded Systems"],"published-print":{"date-parts":[[2002,11]]},"DOI":"10.1023\/a:1020307222052","type":"journal-article","created":{"date-parts":[[2003,3,15]],"date-time":"2003-03-15T08:44:30Z","timestamp":1047717870000},"page":"307-323","source":"Crossref","is-referenced-by-count":35,"title":["Intermediate Representations for Design Automation of Multiprocessor DSP Systems"],"prefix":"10.1007","volume":"7","author":[{"given":"Neal","family":"Bambha","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vida","family":"Kianzad","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mukul","family":"Khandelia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shuvra S.","family":"Bhattacharyya","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"1","key":"5097374_CR1","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1109\/4235.585888","volume":"1","author":"T. Back","year":"1997","unstructured":"Back, T., U. Hammel, and H.-P. Schwefel. Evolutionary Computation: Comments on the History and Current State. IEEE Transactions on Evolutionary Computation, vol. 1, no.1 pp.3-17, April 1997.","journal-title":"IEEE Transactions on Evolutionary Computation"},{"key":"5097374_CR2","doi-asserted-by":"crossref","unstructured":"Bambha, N. K., and S. S. Bhattacharyya. A Joint Power\/Performance OptimizationTechnique for Multiprocessor Systems Using a Period Graph Construct. In Proceedings of the International Symposium on Systems Synthesis, pp. 91\u201397, Sept. 2000.","DOI":"10.1109\/ISSS.2000.874034"},{"key":"5097374_CR3","doi-asserted-by":"crossref","unstructured":"Bambha, N. K., S. S. Bhattacharyya, J. Teich, and E. Zitzler. Hybrid Search Strategies for DynamicVoltage Scaling in Embedded Multiprocessors. In Proceedings of the International Workshop on Hardware\/Software Co-Design, pp. 243\u2013248, Copenhagen, Denmark, April 2001.","DOI":"10.1145\/371636.371744"},{"key":"5097374_CR4","doi-asserted-by":"crossref","first-page":"825","DOI":"10.1109\/71.790600","volume":"0","author":"R. C. Correa","year":"1999","unstructured":"Correa, R. C., A. Ferreira, and P. Rebreyend. Scheduling Multiprocessor Tasks with Genetic Algorithms. IEEE Transactions on Parallel and Distributed Systems, vol. 0, pp. 825\u2013837, 1999.","journal-title":"IEEE Transactions on Parallel and Distributed Systems"},{"issue":"10","key":"5097374_CR5","doi-asserted-by":"crossref","first-page":"889","DOI":"10.1109\/43.728912","volume":"17","author":"A. Dasdan","year":"1998","unstructured":"Dasdan, A., and R. K. Gupta. Faster Maximum and Minimum Mean Cycle Algorithms for System-Performance Analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17 no.10 pp. 889\u2013899, Oct. 1998.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"5097374_CR6","doi-asserted-by":"crossref","unstructured":"Khandelia, M., and S. S. Bhattacharyya. Contention-Conscious Transaction Ordering in Embedded Multiprocessors. In Proceedings of the International Conference on Application Specific Systems, Architectures, and Processors, pp. 276\u2013285, Boston, MA, July 2000.","DOI":"10.1109\/ASAP.2000.862398"},{"key":"5097374_CR7","series-title":"Technical Report","doi-asserted-by":"crossref","DOI":"10.21236\/ADA457629","volume-title":"Contention-Conscious Transaction Ordering in Embedded Multiprocessor Systems","author":"M. Khandelia","year":"2000","unstructured":"Khandelia, M., and S. S. Bhattacharyya. Contention-Conscious Transaction Ordering in Embedded Multiprocessor Systems. Technical Report UMIACS-TR-2000-09, Institute for Advanced Computer Studies, University of Maryland at College Park, March 2000. Also Computer Science Technical Report CS-TR-4109."},{"key":"5097374_CR8","doi-asserted-by":"crossref","unstructured":"Kianzad, V., and S. S. Bhattacharyya. Multiprocessor Clustering for Embedded Systems. In Proceedings of the European Conference on Parallel Computing, pp. 697\u2013701, Manchester, United Kingdom, Aug. 2001.","DOI":"10.1007\/3-540-44681-8_99"},{"key":"5097374_CR9","unstructured":"Lee, E. A., and S. Ha. Scheduling Strategies for Multiprocessor Real Time DSP. In Proceedings of the Global Telecommunications Conference, Nov. 1989."},{"key":"5097374_CR10","doi-asserted-by":"crossref","unstructured":"Lee, E. A., and D. G. Messerschmitt. Static Scheduling of Synchronous Dataflow Programs for Digital Signal Processing. IEEE Transactions on Computers, Feb. 1987.","DOI":"10.1109\/TC.1987.5009446"},{"key":"5097374_CR11","doi-asserted-by":"crossref","first-page":"9","DOI":"10.1023\/A:1008113601237","volume":"22","author":"P. Lieverse","year":"1999","unstructured":"Lieverse, P., E. F. Deprettere, A. C. J. Kienhuis, and E. A. DeKock. A Clustering Approach to Explore Grain-Sizes in the Definition of Processing Elements in Dataflow Architectures. Journal of VLSI Signal Processing, vol. 22, pp. 9\u201320, Aug. 1999.","journal-title":"Journal of VLSI Signal Processing"},{"issue":"1\u20132","key":"5097374_CR12","doi-asserted-by":"crossref","first-page":"55","DOI":"10.1016\/0305-0548(80)90014-3","volume":"7","author":"J. N. Morse","year":"1980","unstructured":"Morse, J. N. Reducing the Size of the Nondominated Set: Pruning by Clustering. Computers and Operations Research, vol.7, no.1\u20132, pp. 55\u201366, 1980.","journal-title":"Computers and Operations Research"},{"key":"5097374_CR13","volume-title":"Petri Net Theory and Modeling of Systems","author":"J. L. Peterson","year":"1981","unstructured":"Peterson, J. L. Petri Net Theory and Modeling of Systems. Prentice-Hall Inc., Englewood Cliffs, NJ, 1981."},{"issue":"4","key":"5097374_CR14","doi-asserted-by":"crossref","first-page":"590","DOI":"10.1145\/321479.321485","volume":"15","author":"R. Reiter","year":"1968","unstructured":"Reiter, R. Scheduling Parallel Computations. Journal of the Association for Computing Machinery, vol. 15, no.4, pp. 590\u2013599, Oct. 1968.","journal-title":"Journal of the Association for Computing Machinery"},{"key":"5097374_CR15","unstructured":"Sarkar, V. Partitioning and Scheduling Parallel Programs for Multiprocessors. MIT Press, 1989."},{"key":"5097374_CR16","doi-asserted-by":"crossref","unstructured":"Sih, G. C., and E. Lee. A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures. IEEE Transactions on Parallel and Distributed Systems, vol. 4, no.2, 1993.","DOI":"10.1109\/71.207593"},{"key":"5097374_CR17","unstructured":"Sriram, S., and S. S. Bhattacharyya, Embedded Multiprocessors: Scheduling and Synchronization. Marcel Dekker, Inc., 2000."},{"key":"5097374_CR18","unstructured":"Sriram, S., and E. A. Lee. Determining the Order of Processor Transactions in Statically Scheduled Multiprocessors. Journal of VLSI Signal Processing, March 1997."},{"key":"5097374_CR19","doi-asserted-by":"crossref","first-page":"951","DOI":"10.1109\/71.308533","volume":"5","author":"T. Yang","year":"1994","unstructured":"Yang, T. and, A. Gerasoulis. DSC: Scheduling Parallel Tasks on an Unbounded Number of Processors. IEEE Transactions on Parallel and Distributed Systems, vol. 5, pp. 951\u2013967, 1994.","journal-title":"IEEE Transactions on Parallel and Distributed Systems"}],"container-title":["Design Automation for Embedded Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1020307222052.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1023\/A:1020307222052\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1020307222052.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,14]],"date-time":"2025-07-14T02:32:53Z","timestamp":1752460373000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1023\/A:1020307222052"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,11]]},"references-count":19,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2002,11]]}},"alternative-id":["5097374"],"URL":"https:\/\/doi.org\/10.1023\/a:1020307222052","relation":{},"ISSN":["0929-5585","1572-8080"],"issn-type":[{"type":"print","value":"0929-5585"},{"type":"electronic","value":"1572-8080"}],"subject":[],"published":{"date-parts":[[2002,11]]}}}