{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,7]],"date-time":"2025-06-07T04:03:55Z","timestamp":1749269035897,"version":"3.41.0"},"reference-count":20,"publisher":"Springer Science and Business Media LLC","issue":"6","license":[{"start":{"date-parts":[[2002,12,1]],"date-time":"2002-12-01T00:00:00Z","timestamp":1038700800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2002,12,1]],"date-time":"2002-12-01T00:00:00Z","timestamp":1038700800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Electronic Testing"],"published-print":{"date-parts":[[2002,12]]},"DOI":"10.1023\/a:1020853107381","type":"journal-article","created":{"date-parts":[[2003,3,18]],"date-time":"2003-03-18T20:57:25Z","timestamp":1048021045000},"page":"627-636","source":"Crossref","is-referenced-by-count":0,"title":["An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application"],"prefix":"10.1007","volume":"18","author":[{"given":"Kuen-Jong","family":"Lee","sequence":"first","affiliation":[]},{"given":"Tsung-Chu","family":"Huang","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"5100335_CR1","unstructured":"M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital System Testing and Testable Design, Computer Science Press, 1990."},{"key":"5100335_CR2","doi-asserted-by":"crossref","unstructured":"S. Chakravarty and V.P. Dabholkar, \u201cTwo Techniques for Minimizing Power Dissipation in Scan Circuits During Test Application,\u201d in IEEE Asian Test Symp., 1994, pp. 324\u2013329.","DOI":"10.1109\/ATS.1994.367211"},{"key":"5100335_CR3","doi-asserted-by":"crossref","unstructured":"R.M. Chou, K.K. Saluja, and V.D. Agrawal, \u201cPower Constraint Scheduling of Tests,\u201d in Proc. Conf. on VLSI Design, 1994, pp. 271\u2013274.","DOI":"10.1109\/ICVD.1994.282700"},{"issue":"2","key":"5100335_CR4","doi-asserted-by":"crossref","first-page":"175","DOI":"10.1109\/92.585217","volume":"5","author":"R.M. Chou","year":"1997","unstructured":"R.M. Chou, K.K. Saluja, and V.D. Agrawal, \u201cScheduling Tests for VLSI Systems under Power Constraints,\u201d IEEE Trans. on VLSI Systems, vol. 5, no. 2, pp. 175\u2013185, June 1997.","journal-title":"IEEE Trans. on VLSI Systems"},{"key":"5100335_CR5","doi-asserted-by":"crossref","unstructured":"F. Corno, P. Prinetto, M. Rebaudengo, and M. Sonza Reorda, \u201cA Test Pattern Generation Methodology for Low Power Consumption,\u201d in VLSI Test Symp., 1998, pp. 453\u2013457.","DOI":"10.1109\/VTEST.1998.670912"},{"issue":"12","key":"5100335_CR6","doi-asserted-by":"crossref","first-page":"1325","DOI":"10.1109\/43.736572","volume":"17","author":"V. Dabholkar","year":"1998","unstructured":"V. Dabholkar, S. Chakravarty, I. Pomeranz, and S. Reddy, \u201cTechniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application,\u201d IEEE Trans. on Computer-Aided Design, vol. 17, no. 12, pp. 1325\u20131333, December 1998.","journal-title":"IEEE Trans. on Computer-Aided Design"},{"key":"5100335_CR7","unstructured":"E.B. Eichelberger and T.W. Williams, \u201cA Logic Design Structure for LSI Testing,\u201d in Proc. Design Automation Conf., 1977, pp. 462\u2013468."},{"key":"5100335_CR8","doi-asserted-by":"crossref","unstructured":"S. Gerstendorfer and H.-J. Wunderlich, \u201cMinimized Power Consumption for Scan-Based BIST,\u201d in Int'l Test Conf., 1999, pp. 77\u201384.","DOI":"10.1109\/TEST.1999.805616"},{"key":"5100335_CR9","doi-asserted-by":"crossref","unstructured":"P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, \u201cCircuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption,\u201d in Asian Test Symp., 1999, pp.89\u201394.","DOI":"10.1109\/ATS.1999.810734"},{"key":"5100335_CR10","doi-asserted-by":"crossref","unstructured":"P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, \u201cA TestVector Inhibiting Technique for LowEnergy BIST Design,\u201d in VLSI Test Symp., 1999, pp. 407\u2013412.","DOI":"10.1109\/VTEST.1999.766696"},{"issue":"21","key":"5100335_CR11","doi-asserted-by":"crossref","first-page":"1752","DOI":"10.1049\/el:19971225","volume":"33","author":"P. Girard","year":"1997","unstructured":"P. Girard, C. Landrault, S. Pravossoudovitch, and D. Severac, \u201cReduction of Power Consumption During Test Application by Test Vector Ordering,\u201d Electronics Letters, vol. 33, no. 21, pp. 1752\u20131754, October 1997.","journal-title":"Electronics Letters"},{"key":"5100335_CR12","doi-asserted-by":"crossref","unstructured":"C.T. Glover and M.R. Mercer, \u201cA Method of Delay Fault Test Generation,\u201d in Proc. Design Automation Conf., 1988, pp. 83\u201390.","DOI":"10.1109\/DAC.1988.14740"},{"key":"5100335_CR13","doi-asserted-by":"crossref","unstructured":"R. Gupta, R. Gupta, and M.A. Breuer, \u201cBALLAST: A Methodology for Partial Scan Design,\u201d in Proc. Int'l. Symp. on Fault-Tolerant Computing, 1989, pp. 118\u2013125.","DOI":"10.1109\/FTCS.1989.105553"},{"key":"5100335_CR14","unstructured":"T.-C. Huang and K.-J. Lee, \u201cAn Input Control Technique for Power Reduction in Scan Circuits During Test Application,\u201d in The Eighth Asian Test Symposium, 1999, pp. 315\u2013320."},{"key":"5100335_CR15","doi-asserted-by":"crossref","unstructured":"Lee Whetsel, \u201cAddressable Test Ports\u2014an Approach to Testing Embedded Cores,\u201d in Int'l Test Conf., 1999, pp. 1055\u20131064.","DOI":"10.1109\/TEST.1999.805839"},{"issue":"12","key":"5100335_CR16","doi-asserted-by":"crossref","first-page":"1793","DOI":"10.1109\/43.811328","volume":"18","author":"K.-J. Lee","year":"1999","unstructured":"K.-J. Lee, J.-J. Chen, and C.-H. Huang, \u201cBroadcasting Test Patterns to Multiple Circuits,\u201d IEEE Trans. on CAD, vol. 18, no. 12, pp. 1793\u20131802, December 1999.","journal-title":"IEEE Trans. on CAD"},{"key":"5100335_CR17","doi-asserted-by":"crossref","unstructured":"K.-J. Lee, M.-H. Lu, and J.-F. Wang, \u201cA Systematic Method to Classify Scan Cells,\u201d in Asian Test Symp., 1993, pp. 219\u2013224.","DOI":"10.1109\/ATS.1993.398808"},{"key":"5100335_CR18","unstructured":"S. Wang and S.K. Gupta, \u201cDS-LFSR:ANewBIST TPG for Low Heat Dissipation,\u201d in Int'l Test Conf., 1997, pp. 848\u2013857."},{"key":"5100335_CR19","doi-asserted-by":"crossref","unstructured":"S. Wang and S.K. Gupta, \u201cLT-RTPG:ANewTest-Per-Scan BIST TPG for LowHeat Dissipation,\u201d in Int'l Test Conf., 1999, pp. 85\u201394.","DOI":"10.1109\/TEST.1999.805617"},{"key":"5100335_CR20","unstructured":"Y. Zorian, \u201cA Distributed BIST Control Scheme for Complex VLSI Devices,\u201d in VLSI Test Symp., 1993, pp. 4\u20139. Kuen-Jong Lee received the BS degree in electrical engineering from the National Taiwan University, Taiwan in 1981, the M.S. degree in electrical and computer engineering from the University of Iowa, USA in 1986, and the PhD degree in electrical engineering 636 Lee and Huang from the University of Southern California, Los Angeles, USA in 1991. He joined the faculty of the National Cheng-Kung University, Tainan, Taiwan in 1991 and is currently a Professor in the Department of Electrical Engineering. He is interested in many aspects of the design and test of digital and analog circuits. Currently his research mainly focuses on the design and testing of system-on-a-chip and mixed-signal circuits. Dr. Lee has served in the technical program committee in a number conferences and symposiums. He is a member of the Steering Committee of Asian Test Symposium (ATS) and is a program co-chair of the 2000 ATS. Professor Lee also serves as the General Chair of the 2002 VLSI Design\/CAD Symposium in Taiwan. Tsung-Chu Huang received his B.S. degree in electrical engineering from the National Taiwan University, Taiwan in 1986, the M.S. degree in electrical engineering from the University of Southern California, USA in 1991, and the PhD degree in electrical engineering from the National Cheng Kong University, Taiwan in 2002. Now he is with Chung Chou Institute of Technology, Taiwan. His interests include low power testing, IDDQ testing and FPGA prototyping."}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1020853107381.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1023\/A:1020853107381\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1020853107381.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:05:36Z","timestamp":1749204336000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1023\/A:1020853107381"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,12]]},"references-count":20,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2002,12]]}},"alternative-id":["5100335"],"URL":"https:\/\/doi.org\/10.1023\/a:1020853107381","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2002,12]]}}}