{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:55:40Z","timestamp":1759146940358,"version":"3.41.0"},"reference-count":17,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2003,8,1]],"date-time":"2003-08-01T00:00:00Z","timestamp":1059696000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2003,8,1]],"date-time":"2003-08-01T00:00:00Z","timestamp":1059696000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Electronic Testing"],"published-print":{"date-parts":[[2003,8]]},"DOI":"10.1023\/a:1024604412648","type":"journal-article","created":{"date-parts":[[2003,9,15]],"date-time":"2003-09-15T21:37:08Z","timestamp":1063661828000},"page":"481-490","source":"Crossref","is-referenced-by-count":2,"title":["Investigations for Minimum Invasion Digital Only Built-In \u201cRamp\u201d Based Test Techniques for Charge Pump PLL's"],"prefix":"10.1007","volume":"19","author":[{"given":"Martin John","family":"Burbidge","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Frederic","family":"Poullet","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jim","family":"Tijou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andrew","family":"Richardson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"5138466_CR1","unstructured":"F. Azais, M. Renovell, Y. Bertrand, A. Ivanov, and S. Tabatabaei, \u201cA Unified in Digital Test Technique for PLL's; Catastropic Faults Covered,\u201d in Proc 5th IMSTW, June 1999."},{"key":"5138466_CR2","unstructured":"D. Banerjee, PLL Performance Simulation and Design, Copyright 1998 National Semiconductors, http:\/\/www.national.com."},{"key":"5138466_CR3","unstructured":"R. Best, Phase Locked Loops, Design Simulation and Applications, 4th edition, Mc-Graw-Hill, ISBN 0071349030."},{"key":"5138466_CR4","unstructured":"M. Burbidge, A. Richardson, and A. Lechner, \u201cTest Techniques for Embedded Charge Pump PLL's; Problems, Current BIST Techniques, and Alternative Suggestions,\u201d in Proc 7th IMSTW, 2001, pp. 97-103."},{"key":"5138466_CR5","doi-asserted-by":"crossref","unstructured":"A. Chan and G.W. Roberts, \u201cA Synthesizeable, Fast And High-Resolution Timing Measurement Device Using A Component-Invariant Vernier Delay Line,\u201d in Proc. ITC01 Proc., 2001, pp. 858-867.","DOI":"10.1109\/TEST.2001.966708"},{"key":"5138466_CR6","doi-asserted-by":"crossref","unstructured":"M. Dalmia, A. Ivanov, and S. Tabatabaei, \u201cPower Supply Current Monitoring Techniques for Testing PLL's,\u201d in Proc. Asian Test Symposium, 1997, pp. 366-371.","DOI":"10.1109\/ATS.1997.643984"},{"key":"5138466_CR7","unstructured":"A. DeHon, \u201cIn-System Timing Extraction and Control Through Scan-Based, Test-Access Ports,\u201d M.I.T. Transit Project, Transit Note No. 102, 1994."},{"key":"5138466_CR8","unstructured":"Fluence, \u201cVCOBIST,\u201d IEEE DAC, June 1999. http:\/\/www.fluence.com\/bistmaxx\/presentvco\/index.htm."},{"key":"5138466_CR9","doi-asserted-by":"crossref","unstructured":"F.M. Gardner, \u201cCharge-Pump Phase-Lock Loops,\u201d IEEE Trans. Comm., pp. 1849-1858, 28th Nov. 1980.","DOI":"10.1109\/TCOM.1980.1094619"},{"issue":"2","key":"5138466_CR10","doi-asserted-by":"crossref","first-page":"86","DOI":"10.1109\/54.844337","volume":"17","author":"K. Jenkins","year":"2000","unstructured":"K. Jenkins and J. Eckhardt, \u201cMeasuring Jitter and Phase Error in Microprocessor Phase-Locked Loops,\u201d IEEE Design and Test of Computers, Vol. 17, Issue 2, pp. 86-93, April-June 2000.","journal-title":"IEEE Design and Test of Computers"},{"key":"5138466_CR11","doi-asserted-by":"crossref","unstructured":"S. Kim and M. Soma, \u201cAn Effective Defect-Oriented BIST Architecture for High Speed Phase Locked Loops,\u201d in Proc. IEEE VLSI Test Symposium, April 2000, pp. 231-236.","DOI":"10.1109\/VTEST.2000.843850"},{"key":"5138466_CR12","doi-asserted-by":"crossref","unstructured":"P. Larson, \u201cMeasurements and Analysis of PLL Jitter Caused by Digital Switching Noise,\u201d IEEE Journal of Solid-State Circuits, pp. 1113-1120, July 2001.","DOI":"10.1109\/4.933469"},{"key":"5138466_CR13","doi-asserted-by":"crossref","unstructured":"B. Razavi (Ed.), Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design, IEEE Press 1996, ISBN 0780311493.","DOI":"10.1109\/9780470545331"},{"key":"5138466_CR14","unstructured":"G.W. Roberts, M. Hafed, and N. Abraskharoun, \u201cA Stand Alone Integrated Test Core For Time And Frequency Based Measurements,\u201d in Proc. Int. Test Conf., 2000, pp. 1031-1041."},{"key":"5138466_CR15","unstructured":"M. Sachdev, Defect Oriented Testing for CMOS Analog and Digital Circuits, Kluwer Academic Publishers, pp. 37-38 and 79-81, 1998."},{"key":"5138466_CR16","doi-asserted-by":"crossref","unstructured":"S. Sunter and A. Roy, \u201cBIST for Phased Locked Loops in Digital Applications,\u201d in Proc. IEEE ITC99, 1999, pp. 532-540.","DOI":"10.1109\/TEST.1999.805777"},{"key":"5138466_CR17","unstructured":"S. Tabatabaei and A. Ivanov, \u201cAn Embedded Core for High-Accuracy Testing of IC Timing Circuit Verifications,\u201d in Proc. 8th IMSTW, June 2002, pp. 227-237."}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1024604412648.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1023\/A:1024604412648\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1024604412648.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:07:43Z","timestamp":1749204463000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1023\/A:1024604412648"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003,8]]},"references-count":17,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2003,8]]}},"alternative-id":["5138466"],"URL":"https:\/\/doi.org\/10.1023\/a:1024604412648","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2003,8]]}}}