{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:40:08Z","timestamp":1749206408490,"version":"3.41.0"},"reference-count":34,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2002,4,1]],"date-time":"2002-04-01T00:00:00Z","timestamp":1017619200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2002,4,1]],"date-time":"2002-04-01T00:00:00Z","timestamp":1017619200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Electronic Testing"],"published-print":{"date-parts":[[2002,4]]},"DOI":"10.1023\/a:1014997610714","type":"journal-article","created":{"date-parts":[[2002,12,28]],"date-time":"2002-12-28T21:55:50Z","timestamp":1041112550000},"page":"179-187","source":"Crossref","is-referenced-by-count":0,"title":["RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage"],"prefix":"10.1007","volume":"18","author":[{"given":"M.B.","family":"Santos","sequence":"first","affiliation":[]},{"given":"F.M.","family":"Gon\u00e7alves","sequence":"additional","affiliation":[]},{"given":"I.C.","family":"Teixeira","sequence":"additional","affiliation":[]},{"given":"J.P.","family":"Teixeira","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"394994_CR1","unstructured":"T.R. Alcaide, \u201cModelado de Fallos y Estimaci\u00f3n de los Processos de Validaci\u00f3n Funcional de Circuitos Digitales Descritos en VHDL Sintetizable,\u201d Ph.D. Thesis, Escuela T\u00e9c. Sup. Ing. Industriales, U.P. Madrid, 1996."},{"key":"394994_CR2","unstructured":"G. Al Hayek and Ch. Robach, \u201cFrom Specification Validation to Hardware Testing: a Unified Method,\u201d in Proc. Int. Test Conf. (ITC), 1996."},{"key":"394994_CR3","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-3606-2","volume-title":"Assessing Fault Model and Test Quality","author":"K.M. Butler","year":"1992","unstructured":"K.M. Butler and M.R. Mercer, \u201cAssessing Fault Model and Test Quality,\u201d Dordrecht: Kluwer Academic, 1992."},{"issue":"7","key":"394994_CR4","doi-asserted-by":"crossref","first-page":"920","DOI":"10.1109\/43.293949","volume":"13","author":"V. Chickermane","year":"1994","unstructured":"V. Chickermane, J. Lee, and J.K. Patel, \u201cAddressing Design for Testability at the Architectural Level,\u201d IEEE Transactions on CAD of Int. Circs. and Syst., vol. 13, no. 7, pp. 920\u2013934, 1994.","journal-title":"IEEE Transactions on CAD of Int. Circs. and Syst"},{"key":"394994_CR5","doi-asserted-by":"crossref","unstructured":"Chung-Hsing and D.G. Saab, \u201cA Novel Behavioral Testability Measure,\u201d96 IEEE Trans. on Computer Aided Design of Int. Circ. and Syst., vol. 12, no. 12, Dec. 1993.","DOI":"10.1109\/43.251159"},{"key":"394994_CR6","unstructured":"CMUDSP benchmark (I-99-5, ITC 99 5), http:\/\/www.ece.cmu. edu\/~lowpower\/benchmarks.html"},{"key":"394994_CR7","doi-asserted-by":"crossref","unstructured":"F. Corno, M. Sonza Reorda, and P. Prinetto, \u201cTestability Analysis and ATPG on Behavioral RT-level VHDL,\u201d in Proc. Int. Test Conf. (ITC), 1997.","DOI":"10.1109\/TEST.1997.639688"},{"key":"394994_CR8","doi-asserted-by":"crossref","unstructured":"F. Fallah, S. Devadas, and K. Keutzer, \u201cOCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification,\u201d in Proc. Design Automation Conf. (DAC), 1998, pp. 152\u2013157.","DOI":"10.1145\/277044.277078"},{"key":"394994_CR9","doi-asserted-by":"crossref","unstructured":"F. Ferrandi, F. Fummi, and D. Sciuto, \u201cImplicit Test Generation for Behavioral VHDL Models,\u201d in Proc. Int. Test Conf. (ITC), 1998, pp. 587\u2013596.","DOI":"10.1109\/TEST.1998.743202"},{"key":"394994_CR10","doi-asserted-by":"crossref","unstructured":"M.H. Gentil, D. Crestani, A. El Rhalibi, and C. Durant, \u201cANew Testability Measure: Description and Evaluation,\u201d in Proc. IEEE VLSI Test Symp. (VTS), 1994, pp. 421\u2013426.","DOI":"10.1109\/VTEST.1994.292279"},{"key":"394994_CR11","unstructured":"Xinli Gu, Krzysztof Kuchcinski, and Zebo Peng, \u201cTestability Analysis and Improvement from VHDL Behavioral Specifications,\u201d in Proc. EuroDAC, 1994, pp. 644\u2013649."},{"key":"394994_CR12","doi-asserted-by":"crossref","unstructured":"H. Hao and E.J. McCluskey, \u201cVery-Low Voltage Testing for Weak CMOS Logic Ics,\u201d in Proc. Int. Test Conf. (ITC), 1993, pp. 275\u2013284.","DOI":"10.1109\/TEST.1993.470686"},{"key":"394994_CR13","doi-asserted-by":"crossref","unstructured":"R.J. Hayne and B.W. Johnson, \u201cBehavioral Fault Modeling in a VHDL Synthesis Environment,\u201d in Proc. Int. Test Conf. (ITC), 1999, pp. 333\u2013340.","DOI":"10.1109\/VTEST.1999.766684"},{"issue":"11","key":"394994_CR14","doi-asserted-by":"crossref","first-page":"1312","DOI":"10.1109\/12.544489","volume":"45","author":"H. Yuan-Chieh","year":"1996","unstructured":"Yuan-Chieh Hsu and S.K. Gupta, \u201cA Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits,\u201d IEEE Transactions on Computers, vol. 45, no. 11, pp. 1312\u20131318, Nov. 1996.","journal-title":"IEEE Transactions on Computers"},{"key":"394994_CR15","unstructured":"M.A. Iyer, moderator org., \u201cHigh Time for High-Level ATPG,\u201d Panel 1 session, in Proc. Int. Test Conf. (ITC), 1999, pp. 1113\u20131119."},{"key":"394994_CR16","unstructured":"P. Maxwell, I. Hartanto, and L. Bentz, \u201cComparing Functional and Structural Tests,\u201d in Proc. Int. Test Conf. (ITC), 2000, pp. 400\u2013407."},{"key":"394994_CR17","doi-asserted-by":"crossref","unstructured":"S.D. Milllman and E.J. McCluskey, \u201cDetecting Bridging Faults with Stuck-at Test Sets,\u201d in Proc. Int. Test Conf. (ITC), 1988, pp. 773\u2013783.","DOI":"10.1109\/TEST.1988.207864"},{"key":"394994_CR18","doi-asserted-by":"crossref","unstructured":"W. Moore, G. Gronthoud, K. Baker, and M. Lousberg, \u201cDelay Fault Testing and Defects in Deep Sub-micron ICs\u2013\u2013Does Critical Resistance Really Mean Anything?,\u201d in Proc. Int. Test Conf. (ITC), 2000, pp. 95\u2013104.","DOI":"10.1109\/TEST.2000.894196"},{"key":"394994_CR19","doi-asserted-by":"crossref","unstructured":"C. Papachristou and C. Carletta, \u201cTest Synthesis in the Behavioral Domain,\u201d in Proc. Int. Test Conf. (ITC), 1995, pp. 693\u2013702.","DOI":"10.1109\/TEST.1995.529899"},{"key":"394994_CR20","unstructured":"M.B. Santos, J. Braga, P. Coimbr\u00e3o, J.P. Teixeira, S. Manich, and L. Balado, \u201cRTL Guided Random-Pattern-Resistant Fault Detection and Low Energy BIST,\u201d in Proc. IEEE Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2001, pp. 37\u201343."},{"key":"394994_CR21","doi-asserted-by":"crossref","unstructured":"M.B. Santos, F.M. Gon\u00e7alves, I.C. Teixeira, and J.P. Teixeira, \u201cDefect-OrientedVerilog Fault Simulation of SoC Macros using a Stratified Fault SamplingTechnique,\u201d in Proc. of the IEEE VLSI Test Symp. (VTS), 1999, pp. 326\u2013332.","DOI":"10.1109\/VTEST.1999.766683"},{"issue":"3","key":"394994_CR22","first-page":"311","volume":"17","author":"M.B. Santos","year":"2000","unstructured":"M.B. Santos, F.M. Gon\u00e7alves, I.M. Teixeira, and J.P. Teixeira, \u201cRTL-based Functional Test Generation for High Defect Coverage in Digital Systems,\u201d Journal of Electronic Testing and Applications (JETTA), vol. 17, no. 3, pp. 311\u2013319, 2000. RTL Design Validation, DFT and Test Pattern Generation 187","journal-title":"Journal of Electronic Testing and Applications (JETTA)"},{"key":"394994_CR23","unstructured":"S. Sengupta, S. Kundu, S. Chakravarty, P. Parvathala, R. Galivanche, G. Kosonocky, M. Rodgers, and T.M. Mak, \u201cDefect-Based Test: a Key Enabler for Success Migration to Structural Test,\u201d Intel Technology Journal, Q1'99, http:\/\/ www.developer.intel.com\/ITJ, 1999."},{"issue":"10","key":"394994_CR24","doi-asserted-by":"crossref","first-page":"1286","DOI":"10.1109\/43.541448","volume":"15","author":"J.J.T. Sousa","year":"1996","unstructured":"J.J.T. Sousa, F.M. Gon\u00e7alves, J.P. Teixeira, C. Marzocca, F. Corsi, and T.W. Williams, \u201cDefect Level Evaluation in an IC Design Environment,\u201d IEEE Trans. on CAD, vol. 15, no. 10, pp. 1286\u20131293, 1996.","journal-title":"IEEE Trans. on CAD"},{"key":"394994_CR25","doi-asserted-by":"crossref","unstructured":"P.A. Thaker, V.D. Agrawal, and M.E. Zaghloul, \u201cValidationVector Grade (VVG): A New Coverage Metric for Validation and Test,\u201d in Proc. IEEE VLSI Test Symp. (VTS), 1999, pp. 182\u2013188.","DOI":"10.1109\/VTEST.1999.766663"},{"key":"394994_CR26","doi-asserted-by":"crossref","unstructured":"P.A. Thaker, V.D. Agrawal, and M.E. Zaghloul, \u201cRegister-Transfer Level Fault Modeling and Test Evaluation Techniques for VLSI Circuits,\u201d in Proc. Int. Test Conf. (ITC), 2000, pp. 940\u2013949.","DOI":"10.1109\/TEST.2000.894305"},{"key":"394994_CR27","doi-asserted-by":"crossref","unstructured":"K. Thearling and J. Abraham, \u201cAnEasily Functional LevelTestability Measure,\u201d in Proc. Int. Test Conf. (ITC), 1989, pp. 381\u2013390.","DOI":"10.1109\/TEST.1989.82322"},{"key":"394994_CR28","unstructured":"The Torch processor benchmark, http:\/\/www-flash.stanford. edu:80\/torch\/"},{"key":"394994_CR29","doi-asserted-by":"crossref","unstructured":"Yves Le Traon and C. Robach, \u201cFrom Hardware to Software Testability,\u201d in Proc Int.Test Conf, 1995, pp. 710\u2013719.","DOI":"10.1109\/TEST.1995.529901"},{"key":"394994_CR30","doi-asserted-by":"crossref","unstructured":"M. Vahid and A.6Orailoglu, \u201cTestability Metrics for Synthesis of Self-Testable Designs and Effective Test Plans,\u201d in Proc. IEEE VLSI Test Symp. (VTS), 1995, pp. 170\u2013175.","DOI":"10.1109\/VTEST.1995.512633"},{"key":"394994_CR31","doi-asserted-by":"crossref","unstructured":"J.R. Wallack and R. Dandapani, \u201cCoverage Metrics for Functional Tests,\u201d in Proc. IEEE VLSI Test Symp. (VTS), 1994, pp. 176\u2013181.","DOI":"10.1109\/VTEST.1994.292317"},{"key":"394994_CR32","doi-asserted-by":"crossref","unstructured":"P.C. Ward and J.R. Armstrong, \u201cBehavioral Fault Simulation in VHDL,\u201d in Proc. 27th. ACM\/IEEE Design Automation Conf. (DAC), 1990, pp. 587\u2013593.","DOI":"10.1145\/123186.123411"},{"key":"394994_CR33","unstructured":"Q. Zhang and I.G.6Harris, \u201cA Domain Coverage Metric for the Validation of Behavioral VHDL Descriptions,\u201d in Proc. Int. Test Conf. (ITC), 2000, pp. 302\u2013308."},{"key":"394994_CR34","doi-asserted-by":"crossref","unstructured":"Y. Zorian, E. Marinissen, and S. Dey, \u201cTesting Embedded-Core Based System Chips,\u201d in Proc. IEEE International Test Conference (ITC), 1998, pp. 130\u2013143.","DOI":"10.1109\/TEST.1998.743146"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1014997610714.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1023\/A:1014997610714\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1014997610714.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:12:41Z","timestamp":1749204761000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1023\/A:1014997610714"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,4]]},"references-count":34,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2002,4]]}},"alternative-id":["394994"],"URL":"https:\/\/doi.org\/10.1023\/a:1014997610714","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2002,4]]}}}