{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,16]],"date-time":"2026-08-16T06:25:32Z","timestamp":1786861532561,"version":"3.56.0"},"reference-count":86,"publisher":"Springer Science and Business Media LLC","issue":"7373","license":[{"start":{"date-parts":[[2011,11,1]],"date-time":"2011-11-01T00:00:00Z","timestamp":1320105600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Nature"],"published-print":{"date-parts":[[2011,11]]},"DOI":"10.1038\/nature10679","type":"journal-article","created":{"date-parts":[[2011,11,15]],"date-time":"2011-11-15T20:16:47Z","timestamp":1321388207000},"page":"329-337","source":"Crossref","is-referenced-by-count":2761,"title":["Tunnel field-effect transistors as energy-efficient electronic switches"],"prefix":"10.1038","volume":"479","author":[{"given":"Adrian M.","family":"Ionescu","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Heike","family":"Riel","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2011,11,16]]},"reference":[{"key":"BFnature10679_CR1","first-page":"429","volume-title":"IEICE Trans. Electron","author":"T Sakurai","year":"2004","unstructured":"Sakurai, T. Perspectives of low power VLSI's. IEICE Trans. Electron E87-C, 429\u2013436 (IEICE, 2004)."},{"key":"BFnature10679_CR2","doi-asserted-by":"publisher","first-page":"2169","DOI":"10.1109\/JPROC.2010.2066530","volume":"98","author":"K Bernstein","year":"2010","unstructured":"Bernstein, K., Cavin, R. K., Porod, W., Seabaugh A. C. & Welser, J. Device and architectures outlook for beyond CMOS switches. Proc. IEEE 98, 2169\u20132184 (2010).","journal-title":"Proc. IEEE"},{"key":"BFnature10679_CR3","doi-asserted-by":"publisher","first-page":"2095","DOI":"10.1109\/JPROC.2010.2070470","volume":"98","author":"AC Seabaugh","year":"2010","unstructured":"Seabaugh, A. C. & Zhang, Q. Low voltage tunnel transistors for beyond CMOS logic. Proc. IEEE 98, 2095\u20132110 (2010).","journal-title":"Proc. IEEE"},{"key":"BFnature10679_CR4","volume-title":"Physics of Semiconductor Devices","author":"SM Sze","year":"1969","unstructured":"Sze, S. M. Physics of Semiconductor Devices, 1st edn (John Wiley, 1969)."},{"key":"BFnature10679_CR5","first-page":"1","volume-title":"Proc. IEEE Int. SOI Conf","author":"MS Lundstrom","year":"2006","unstructured":"Lundstrom, M. S. The MOSFET revisited: device physics and modeling at the nanoscale. Proc. IEEE Int. SOI Conf. 1\u20133 (IEEE, 2006)."},{"key":"BFnature10679_CR6","first-page":"219","volume-title":"Proc. Int. Symp. Low Power Electron. Design","author":"D Kim","year":"2009","unstructured":"Kim, D. et al. Heterojunction tunneling transistor (HETT)-based extremely low power applications. Proc. Int. Symp. Low Power Electron. Design 219\u2013224 (IEEE\/ACM, 2009)."},{"key":"BFnature10679_CR7","doi-asserted-by":"publisher","first-page":"1541","DOI":"10.1109\/TED.2005.850618","volume":"52","author":"K Bhuwalka","year":"2005","unstructured":"Bhuwalka, K., Schultze, J. & Eisele, I. A simulation approach to optimize the electrical parameters of a vertical tunnel FET. IEEE Trans. Electron Devices 52, 1541\u20131547 (2005).","journal-title":"IEEE Trans. Electron Devices"},{"key":"BFnature10679_CR8","doi-asserted-by":"publisher","first-page":"1725","DOI":"10.1109\/TED.2007.899389","volume":"54","author":"K Boucart","year":"2007","unstructured":"Boucart, K. & Ionescu, A. M. Double-gate tunnel FET with high-\u03ba gate dielectric. IEEE Trans. Electron Devices 54, 1725\u20131733 (2007).","journal-title":"IEEE Trans. Electron Devices"},{"key":"BFnature10679_CR9","volume-title":"Tech. Digest IEEE Int. Electron Devices Meet","author":"H Kam","year":"2008","unstructured":"Kam, H., King-Liu, T.-J., Alon, E. & Horowitz, M. Circuit-level requirements for MOSFET-replacement devices. Tech. Digest IEEE Int. Electron Devices Meet. 1 (IEEE, 2008)."},{"key":"BFnature10679_CR10","doi-asserted-by":"publisher","first-page":"175","DOI":"10.1109\/TED.2007.911033","volume":"55","author":"S Hanson","year":"2008","unstructured":"Hanson, S., Seok, M., Sylvester, D. & Blaauw, D. Nanometer device scaling in subthrehold logic and SRAM. IEEE Trans. Electron Devices 55, 175\u2013185 (2008).","journal-title":"IEEE Trans. Electron Devices"},{"key":"BFnature10679_CR11","doi-asserted-by":"publisher","first-page":"215","DOI":"10.1109\/JPROC.2009.2035451","volume":"98","author":"L Chang","year":"2010","unstructured":"Chang, L. et al. Practical strategies for power-efficient computing technologies. Proc. IEEE 98, 215\u2013236 (2010).","journal-title":"Proc. IEEE"},{"key":"BFnature10679_CR12","first-page":"469","volume-title":"Proc. Asia S. Pacif. Design Automat. Conf","author":"K Nose","year":"2000","unstructured":"Nose, K. & Sakurai, T. Optimization of V DD and V TH for low-power and high-speed applications. Proc. Asia S. Pacif. Design Automat. Conf. 469\u2013474 (ACM, 2000)."},{"key":"BFnature10679_CR13","doi-asserted-by":"publisher","first-page":"289","DOI":"10.1109\/IEDM.2002.1175835","volume-title":"Tech. Digest IEEE Int. Electron Devices Meet","author":"K Gopalakrishnan","year":"2002","unstructured":"Gopalakrishnan, K., Griffin, P. B. & Plummer, J. D. I-MOS: a novel semiconductor device with subthreshold slope lower than kT\/q. Tech. Digest IEEE Int. Electron Devices Meet. 289\u2013292 (IEEE, 2002)."},{"key":"BFnature10679_CR14","doi-asserted-by":"publisher","first-page":"523","DOI":"10.1098\/rspa.1934.0116","volume":"145","author":"C Zener","year":"1934","unstructured":"Zener, C. A theory of electrical breakdown of solid dielectrics. Proc. R. Soc. Lond. A 145, 523\u2013529 (1934).","journal-title":"Proc. R. Soc. Lond. A"},{"key":"BFnature10679_CR15","doi-asserted-by":"publisher","first-page":"405","DOI":"10.1021\/nl071804g","volume":"8","author":"S Salahuddin","year":"2008","unstructured":"Salahuddin, S. & Datta, S. Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett. 8, 405\u2013410 (2008).","journal-title":"Nano Lett."},{"key":"BFnature10679_CR16","first-page":"1","volume-title":"Tech. Digest IEEE Int. Electron Devices Meet","author":"GA Salvatore","year":"2008","unstructured":"Salvatore, G. A., Bouvet, D. & Ionescu, A. M. Demonstration of subthreshold swing smaller than 60mV\/decade in Fe-FET with P(VDF-TrFE)\/SiO2 gate stack. Tech. Digest IEEE Int. Electron Devices Meet. 1\u20134 (IEEE, 2008)."},{"key":"BFnature10679_CR17","first-page":"16.3.1","volume-title":"IEEE Int. Electron Devices Meet","author":"A Rusu","year":"2010","unstructured":"Rusu, A., Salvatore, G. A., Jimenez, D. & Ionescu, A. M. Metal-ferroelectric-meta-oxide-semiconductor field effect transistor with sub-60mV\/decade subthreshold swing and internal voltage amplification. IEEE Int. Electron Devices Meet. 16.3.1\u201316.3.4 (IEEE, 2010)."},{"key":"BFnature10679_CR18","first-page":"479","volume-title":"Tech. Digest IEEE Int. Electron Devices Meet","author":"N Abele","year":"2005","unstructured":"Abele, N. et al. Suspended-gate MOSFET: bringing new MEMS functionality into solid-state MOS transistor. Tech. Digest IEEE Int. Electron Devices Meet. 479\u2013481 (IEEE, 2005)."},{"key":"BFnature10679_CR19","first-page":"750","volume-title":"IEEE\/ACM Int. Conf. Computer-Aided Design","author":"F Chen","year":"2008","unstructured":"Chen, F. et al. Integrated circuit design with NEM relays. IEEE\/ACM Int. Conf. Computer-Aided Design 750\u2013757 (IEEE, 2008)."},{"key":"BFnature10679_CR20","doi-asserted-by":"publisher","first-page":"2076","DOI":"10.1109\/JPROC.2010.2063411","volume":"98","author":"V Pott","year":"2010","unstructured":"Pott, V., Hei Kam, N. R., Jaeseok, J., Alon, E. & Tsu-Jae, K. L. Mechanical computing redux: relays for integrated circuit applications. Proc. IEEE 98, 2076\u20132094 (2010).","journal-title":"Proc. IEEE"},{"key":"BFnature10679_CR21","doi-asserted-by":"publisher","first-page":"190","DOI":"10.1016\/0039-6028(78)90489-2","volume":"73","author":"J Quinn","year":"1978","unstructured":"Quinn, J., Kawamoto, G. & McCombe, B. Subband spectroscopy by surface channel tunneling. Surf. Sci. 73, 190\u2013196 (1978).","journal-title":"Surf. Sci."},{"key":"BFnature10679_CR22","doi-asserted-by":"publisher","first-page":"347","DOI":"10.1109\/EDL.1987.26655","volume":"8","author":"S Banerjee","year":"1987","unstructured":"Banerjee, S., Richardson W., Coleman J. & Chatterjee, A. A new three-terminal tunnel device. IEEE Electron Device Lett. 8, 347\u2013349 (1987).","journal-title":"IEEE Electron Device Lett."},{"key":"BFnature10679_CR23","doi-asserted-by":"publisher","first-page":"402","DOI":"10.1109\/IEDM.1988.32841","volume-title":"Tech. Digest IEEE Int. Electron Devices Meet","author":"E Takeda","year":"1988","unstructured":"Takeda, E., Matsuoka, H., Igura, Y. & Asai, S. A band to band tunneling MOS device B2T-MOSFET. Tech. Digest IEEE Int. Electron Devices Meet. 402\u2013405 (IEEE, 1988)."},{"key":"BFnature10679_CR24","doi-asserted-by":"publisher","first-page":"L455","DOI":"10.1143\/JJAP.31.L455","volume":"31","author":"T Baba","year":"1992","unstructured":"Baba, T. Proposal for surface tunnel transistors. Jpn. J. Appl. Phys. 31, L455\u2013L457 (1992).","journal-title":"Jpn. J. Appl. Phys."},{"key":"BFnature10679_CR25","doi-asserted-by":"publisher","first-page":"494","DOI":"10.1063\/1.114547","volume":"67","author":"W Reddick","year":"1995","unstructured":"Reddick, W. & Amaratunga, G. Silicon surface tunnel transistor. Appl. Phys. Lett. 67, 494\u2013496 (1995).","journal-title":"Appl. Phys. Lett."},{"key":"BFnature10679_CR26","doi-asserted-by":"publisher","first-page":"1435","DOI":"10.1063\/1.117606","volume":"69","author":"J Koga","year":"1996","unstructured":"Koga, J. & Toriumi, A. Negative differential conductance in three-terminal silicon tunneling device. Appl. Phys. Lett. 69, 1435\u20131437 (1996).","journal-title":"Appl. Phys. Lett."},{"key":"BFnature10679_CR27","doi-asserted-by":"publisher","first-page":"387","DOI":"10.1016\/S0040-6090(00)00896-8","volume":"369","author":"W Hansch","year":"2000","unstructured":"Hansch, W., Fink, C., Schulze, J. & Eisele, I. A vertical MOS-gated Esaki tunneling transistor in silicon. Thin Solid Films 369, 387\u2013389 (2000).","journal-title":"Thin Solid Films"},{"key":"BFnature10679_CR28","doi-asserted-by":"publisher","first-page":"1780","DOI":"10.1063\/1.1668321","volume":"84","author":"C Aydin","year":"2004","unstructured":"Aydin, C. et al. Lateral interband tunneling transistor in silicon-on-insulator. Appl. Phys. Lett. 84, 1780\u20131782 (2004).","journal-title":"Appl. Phys. Lett."},{"key":"BFnature10679_CR29","doi-asserted-by":"publisher","first-page":"196805","DOI":"10.1103\/PhysRevLett.93.196805","volume":"93","author":"J Appenzeller","year":"2004","unstructured":"Appenzeller, J., Lin, Y.-M., Knoch J. & Avouris, P. Band-to-band tunneling in carbon nanotube field-effect transistors. Phys. Rev. Lett. 93, 196805 (2004).","journal-title":"Phys. Rev. Lett."},{"key":"BFnature10679_CR30","first-page":"947","volume-title":"Tech. Digest IEEE Int. Electron Devices Meet","author":"T Krishnamohan","year":"2008","unstructured":"Krishnamohan, T., Kim, D., Raghunathan, S. & Saraswat, K. Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and <60 mV\/dec subthreshold slope. Tech. Digest IEEE Int. Electron Devices Meet. 947\u2013949 (IEEE, 2008)."},{"key":"BFnature10679_CR31","first-page":"163","volume-title":"Tech. Digest IEEE Int. Electron Devices Meet","author":"F Mayer","year":"2008","unstructured":"Mayer, F. et al. Impact of SOI, Si1\u2013xGexOI and GeOI substrates on CMOS compatible tunnel FET performance. Tech. Digest IEEE Int. Electron Devices Meet. 163\u2013166 (IEEE, 2008)."},{"key":"BFnature10679_CR32","first-page":"16.1.1","volume-title":"IEEE Int. Electron Devices Meet","author":"C Hu","year":"2010","unstructured":"Hu, C. et al. Prospect of tunneling green transistor for 0.1 V CMOS. IEEE Int. Electron Devices Meet. 16.1.1\u201316.1.4 (IEEE, 2010)."},{"key":"BFnature10679_CR33","first-page":"448","volume-title":"Proc. Eur. Solid State Device Res. Conf","author":"KE Moselund","year":"2009","unstructured":"Moselund, K. E. et al. Comparison of VLS grown Si NW tunnel FETs with different gate stacks. Proc. Eur. Solid State Device Res. Conf. 448\u2013451 (IEEE, 2009)."},{"key":"BFnature10679_CR34","doi-asserted-by":"publisher","first-page":"2281","DOI":"10.1016\/j.sse.2004.04.006","volume":"48","author":"PF Wang","year":"2004","unstructured":"Wang, P. F. et al. Complementary tunneling transistor for low power application. Solid-State Electron. 48, 2281\u20132286 (2004).","journal-title":"Solid-State Electron."},{"key":"BFnature10679_CR35","first-page":"153","volume-title":"Digest Device Res. Conf","author":"J Knoch","year":"2006","unstructured":"Knoch, J. & Appenzeller, J. A novel concept for field-effect transistors \u2013 the tunneling carbon nanotube FET. Digest Device Res. Conf. 153\u2013156 (IEEE, 2006)."},{"key":"BFnature10679_CR36","doi-asserted-by":"publisher","first-page":"572","DOI":"10.1016\/j.sse.2007.02.001","volume":"51","author":"J Knoch","year":"2007","unstructured":"Knoch, J., Mantl, S. & Appenzeller, J. Impact of the dimensionality on the performance of tunneling FETs: bulk versus one-dimensional devices. Solid-State Electron. 51, 572\u2013578 (2007).","journal-title":"Solid-State Electron."},{"key":"BFnature10679_CR37","doi-asserted-by":"publisher","first-page":"297","DOI":"10.1109\/LED.2006.871855","volume":"27","author":"Q Zhang","year":"2006","unstructured":"Zhang, Q., Zhao, W. & Seabaugh, A. Low-subthreshold-swing tunnel transistors. IEEE Electron Device Lett. 27, 297\u2013300 (2006).","journal-title":"IEEE Electron Device Lett."},{"key":"BFnature10679_CR38","doi-asserted-by":"publisher","first-page":"084507","DOI":"10.1063\/1.3386521","volume":"107","author":"M Luisier","year":"2010","unstructured":"Luisier, M. & Klimeck, G. Simulation of nanowire tunneling transistors: from the Wentzel\u2013Kramers\u2013Brillouin approximation to full-band phonon-assisted tunneling. J. Appl. Phys. 107, 084507 (2010).","journal-title":"J. Appl. Phys."},{"key":"BFnature10679_CR39","doi-asserted-by":"publisher","first-page":"2827","DOI":"10.1109\/TED.2008.2008011","volume":"55","author":"J Appenzeller","year":"2008","unstructured":"Appenzeller, J., Knoch, J., Bj\u00f6rk, M. T., Riel, H. & Riess, W. Toward nanowire electronics. IEEE Trans. Electron Devices 55, 2827\u20132845 (2008).","journal-title":"IEEE Trans. Electron Devices"},{"key":"BFnature10679_CR40","unstructured":"Ionescu, A. M., Boucart, K., Moselund, K. E. & Pott, V. Small Swing Switches (Cambridge Univ. Press, in the press)."},{"key":"BFnature10679_CR41","first-page":"170","volume-title":"Proc. Eur. Solid State Device Res. Conf","author":"D Leonelli","year":"2010","unstructured":"Leonelli, D. et al. Optimization of tunnel FETs: impact of gate oxide thickness, implantation and annealing conditions. Proc. Eur. Solid State Device Res. Conf. 170\u2013173 (IEEE, 2010)."},{"key":"BFnature10679_CR42","doi-asserted-by":"publisher","first-page":"1500","DOI":"10.1016\/j.sse.2007.09.014","volume":"51","author":"K Boucart","year":"2007","unstructured":"Boucart, K. & Ionescu, A. M. Length scaling of the double gate tunnel FET with a high-\u03ba gate dielectric. Solid State Electron. 51, 1500\u20131507 (2007).","journal-title":"Solid State Electron."},{"key":"BFnature10679_CR43","doi-asserted-by":"publisher","first-page":"1126","DOI":"10.1016\/j.sse.2009.05.009","volume":"53","author":"C Sandow","year":"2009","unstructured":"Sandow, C., Knoch, J., Urban, C., Zhao, Q.-T. & Mantl, S. Impact of electrostatics and doping concentration on the performance of silicon tunnel field-effect transistors. Solid State Electron. 53, 1126\u20131129 (2009).","journal-title":"Solid State Electron."},{"key":"BFnature10679_CR44","doi-asserted-by":"publisher","first-page":"4073","DOI":"10.1143\/JJAP.43.4073","volume":"43","author":"K Bhuwalka","year":"2004","unstructured":"Bhuwalka, K., Schulze, J. & Eisele, I. Performance enhancement of vertical tunnel field-effect transistor with SiGe in the dp+ layer. Jpn. J. Appl. Phys. 43, 4073\u20134078 (2004).","journal-title":"Jpn. J. Appl. Phys."},{"key":"BFnature10679_CR45","doi-asserted-by":"publisher","first-page":"1398","DOI":"10.1109\/LED.2008.2007599","volume":"29","author":"A Verhulst","year":"2008","unstructured":"Verhulst, A. et al. Complementary silicon-based heterostructure tunnel-FETs with high tunnel rates. IEEE Electron Device Lett. 29, 1398\u20131401 (2008).","journal-title":"IEEE Electron Device Lett."},{"key":"BFnature10679_CR46","first-page":"45","volume-title":"Int. Symp. VLSI-TSA","author":"J Knoch","year":"2009","unstructured":"Knoch, J. Optimizing tunnel FET performance\u2013impact of device structure, transistor dimensions and choice of material. Int. Symp. VLSI-TSA 45\u201346 (IEEE, 2009)."},{"key":"BFnature10679_CR47","doi-asserted-by":"publisher","first-page":"305","DOI":"10.1109\/LED.2010.2041180","volume":"31","author":"J Knoch","year":"2010","unstructured":"Knoch, J. & Appenzeller, J. Modeling of high-performance p-type III\u2013V heterojunction tunnel FETs. IEEE Electron Device Lett. 31, 305\u2013307 (2010).","journal-title":"IEEE Electron Device Lett."},{"key":"BFnature10679_CR48","doi-asserted-by":"publisher","first-page":"3222","DOI":"10.1109\/TED.2010.2079250","volume":"57","author":"SO Koswatta","year":"2010","unstructured":"Koswatta, S. O., Koester, S. J. & Haensch, W. On the possibility of obtaining MOSFET-like performance and sub-60-mV\/dec swing in 1-D broken-gap tunnel transistors. IEEE Trans. Electron Devices 57, 3222\u20133223 (2010).","journal-title":"IEEE Trans. Electron Devices"},{"key":"BFnature10679_CR49","first-page":"16","volume-title":"Proc. 9th Int. Conf. Solid-State Integrated-Circuit Technol","author":"C Hu","year":"2008","unstructured":"Hu, C. Green transistor as a solution to the IC power crisis. Proc. 9th Int. Conf. Solid-State Integrated-Circuit Technol. 16\u201320 (IEEE, 2008)."},{"key":"BFnature10679_CR50","first-page":"16.1.1","volume-title":"IEEE Int. Electron Devices Meet","author":"C Hu","year":"2010","unstructured":"Hu, C. et al. Prospect of tunneling green transistor for 0.1 V CMOS. IEEE Int. Electron Devices Meet. 16.1.1\u201316.1.4 (IEEE, 2010)."},{"key":"BFnature10679_CR51","doi-asserted-by":"publisher","first-page":"1855","DOI":"10.1109\/TED.2011.2140322","volume":"58","author":"R Asra","year":"2011","unstructured":"Asra, R. et al. A tunnel FET for V DD scaling below 0.6V with a CMOS-comparable performance. IEEE Trans. Electron Devices 58, 1855\u20131863 (2011).","journal-title":"IEEE Trans. Electron Devices"},{"key":"BFnature10679_CR52","unstructured":"De Michielis, L., Lattanzio, L., Palestri, P., Selmi L. & Ionescu, A. M. Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier. IEEE Device Res. Conf. (IEEE, in the press)."},{"key":"BFnature10679_CR53","doi-asserted-by":"publisher","first-page":"1074","DOI":"10.1109\/LED.2008.2000970","volume":"29","author":"OM Nayfeh","year":"2008","unstructured":"Nayfeh, O. M. et al. Design of tunneling field-effect transistors using strained-silicon\/strained-germanium type-II staggered heterojunctions. IEEE Electron Device Lett. 29, 1074\u20131077 (2008).","journal-title":"IEEE Electron Device Lett."},{"key":"BFnature10679_CR54","first-page":"452","volume-title":"Proc. Eur. Solid State Device Res. Conf","author":"K Boucart","year":"2009","unstructured":"Boucart, K., Ionescu, A. M. & Riess, W. Asymmetrically strained all-silicon tunnel FETs featuring 1V operation. Proc. Eur. Solid State Device Res. Conf. 452\u2013456 (IEEE, 2009)."},{"key":"BFnature10679_CR55","doi-asserted-by":"publisher","first-page":"656","DOI":"10.1109\/LED.2009.2018127","volume":"30","author":"K Boucart","year":"2009","unstructured":"Boucart, K., Riess, W. & Ionescu, A. M. Lateral strain profile as key technology booster for all-silicon tunnel FETs. IEEE Electron Device Lett. 30, 656\u2013658 (2009).","journal-title":"IEEE Electron Device Lett."},{"key":"BFnature10679_CR56","unstructured":"Boucart, K. Simulation of a Double Gate Silicon Tunnel FET with a High-\u03ba Dielectric. PhD thesis, Ecole Polytechnoique F\u00e9d\u00e9rale de Lausanne (2009)."},{"key":"BFnature10679_CR57","first-page":"53","volume-title":"Proc. 10th Int. Conf. Ultimate Integration Silicon","author":"C Le Royer","year":"2009","unstructured":"Le Royer, C. & Mayer, F. Exhaustive experimental study of tunnel field effect transistors (TFETs): from materials to architecture. Proc. 10th Int. Conf. Ultimate Integration Silicon 53\u201356 (IEEE, 2009)."},{"key":"BFnature10679_CR58","first-page":"162","volume-title":"Proc. Eur. Solid State Device Res. Conf","author":"W-Y Loh","year":"2010","unstructured":"Loh, W.-Y. et al. Sub-60nm Si tunnel field effect transistors with I on > 100 \u03bcA\/ \u03bcm. Proc. Eur. Solid State Device Res. Conf. 162\u2013165 (IEEE, 2010)."},{"key":"BFnature10679_CR59","first-page":"137.1","volume-title":"IEEE Int. Electron Devices Meet","author":"S Mookerjea","year":"2009","unstructured":"Mookerjea, S. et al. Experimental demonstration of 100 nm channel length In0.53Ga0.47As-based vertical inter-band tunnel field effect transistors (TFET) for ultra low-power logic and SRMA applications. IEEE Int. Electron Devices Meet. 137.1\u2013137.4 (IEEE, 2009)."},{"key":"BFnature10679_CR60","doi-asserted-by":"publisher","first-page":"2990","DOI":"10.1109\/TED.2011.2159385","volume":"58","author":"H Zhao","year":"2011","unstructured":"Zhao, H. et al. InGaAs tunneling field-effect transistors with atomic-layer-deposited gate oxides. IEEE Trans. Electron Devices 58, 2990\u20132995 (2011).","journal-title":"IEEE Trans. Electron Devices"},{"key":"BFnature10679_CR61","doi-asserted-by":"publisher","first-page":"564","DOI":"10.1109\/LED.2010.2045631","volume":"31","author":"S Mookerjea","year":"2010","unstructured":"Mookerjea, S., Mohata, D., Mayer, T., Narayanan V. & Datta, S. Temperature-dependent characteristics of a vertical tunnel FET. IEEE Electron Device Lett. 31, 564\u2013566 (2010).","journal-title":"IEEE Electron Device Lett."},{"key":"BFnature10679_CR62","doi-asserted-by":"publisher","first-page":"431","DOI":"10.1109\/LED.2010.2044012","volume":"31","author":"L Wang","year":"2010","unstructured":"Wang, L., Yu, E., Taur Y. & Asbeck, P. Design of tunneling field-effect transistors based on staggered heterojunctions for ultralow-power applications. IEEE Electron Device Lett. 31, 431\u2013433 (2010).","journal-title":"IEEE Electron Device Lett."},{"key":"BFnature10679_CR63","doi-asserted-by":"publisher","first-page":"024105","DOI":"10.1143\/APEX.4.024105","volume":"4","author":"D Mohata","year":"2011","unstructured":"Mohata, D. et al. Experimental staggered-source and N+ pocket-doped channel III\u2013V tunnel field-effect transistors and their scalabilities. Appl. Phys. Express 4, 024105 (2011).","journal-title":"Appl. Phys. Express"},{"key":"BFnature10679_CR64","doi-asserted-by":"publisher","first-page":"205","DOI":"10.1109\/DRC.2011.5994499","volume-title":"IEEE Device Res. Conf","author":"G Zhou","year":"2011","unstructured":"Zhou, G. et al. Self-aligned InAs\/Al0.45Ga0.55Sb vertical tunnel FETs. IEEE Device Res. Conf. 205\u2013206 (IEEE, 2011)."},{"key":"BFnature10679_CR65","doi-asserted-by":"publisher","first-page":"3475","DOI":"10.1021\/nl802398j","volume":"8","author":"K Tomioka","year":"2008","unstructured":"Tomioka, K., Motohisa, J., Hara S. & Fukui, T. Control of InAs nanowire growth directions on Si. Nano Lett. 8, 3475\u20133480 (2008).","journal-title":"Nano Lett."},{"key":"BFnature10679_CR66","doi-asserted-by":"publisher","first-page":"163501","DOI":"10.1063\/1.3499365","volume":"97","author":"MT Bj\u00f6rk","year":"2010","unstructured":"Bj\u00f6rk, M. T. et al. Si\u2013InAs heterojunction Esaki tunnel diodes with high current densities. Appl. Phys. Lett. 97, 163501 (2010).","journal-title":"Appl. Phys. Lett."},{"key":"BFnature10679_CR67","doi-asserted-by":"publisher","first-page":"4195","DOI":"10.1021\/nl202103a","volume":"11","author":"CD Bessire","year":"2011","unstructured":"Bessire, C. D. et al. Trap-assisted tunneling in Si\u2013InAs nanowire heterojunction tunnel diodes. Nano Lett. 11, 4195\u20134199 (2011).","journal-title":"Nano Lett."},{"key":"BFnature10679_CR68","doi-asserted-by":"publisher","first-page":"17","DOI":"10.1109\/DRC.2010.5551905","volume-title":"IEEE Device Res. Conf","author":"Y Lu","year":"2010","unstructured":"Lu, Y. et al. Geometry dependent tunnel FET performance \u2014 dilemma of electrostatics vs. quantum confinement. IEEE Device Res. Conf. 17\u201318 (IEEE, 2010)."},{"key":"BFnature10679_CR69","doi-asserted-by":"crossref","unstructured":"Schmid, H. et al. Fabrication of vertical InAs\u2013Si heterojunction tunnel field effect transistors. IEEE Proc. Device Res. Conf. 181\u2013182 (2011).","DOI":"10.1109\/DRC.2011.5994479"},{"key":"BFnature10679_CR70","doi-asserted-by":"publisher","first-page":"313","DOI":"10.1109\/TED.2007.910563","volume":"55","author":"S Poli","year":"2008","unstructured":"Poli, S. et al. Computational study of the ultimate scaling limits of CNT tunneling devices. IEEE Trans. Electron Devices 55, 313\u2013321 (2008).","journal-title":"IEEE Trans. Electron Devices"},{"key":"BFnature10679_CR71","doi-asserted-by":"publisher","first-page":"1160","DOI":"10.1021\/nl062843f","volume":"7","author":"SO Koswatta","year":"2007","unstructured":"Koswatta, S. O., Lundstrom, M. S. & Nikonov, D. E. Band-to-band tunneling in a carbon nanotube metal-oxide-semiconductor field-effect transistor is dominated by phonon-assisted tunneling. Nano Lett. 7, 1160\u20131164 (2007).","journal-title":"Nano Lett."},{"key":"BFnature10679_CR72","doi-asserted-by":"publisher","first-page":"2568","DOI":"10.1109\/TED.2005.859654","volume":"52","author":"J Appenzeller","year":"2005","unstructured":"Appenzeller, J., Lin, Y.-M., Knoch, J., Chen, Z. & Avouris, P. Comparing carbon nanotube transistors \u2014 the ideal choice: a novel tunneling device design. IEEE Trans. Electron Devices 52, 2568\u20132576 (2005).","journal-title":"IEEE Trans. Electron Devices"},{"key":"BFnature10679_CR73","doi-asserted-by":"publisher","first-page":"627","DOI":"10.1038\/nphys1022","volume":"4","author":"Y Zhang","year":"2008","unstructured":"Zhang, Y. et al. Giant phonon-induced conductance in scanning tunneling spectroscopy of gate-tunable graphene. Nature Phys. 4, 627\u2013630 (2008).","journal-title":"Nature Phys."},{"key":"BFnature10679_CR74","first-page":"201","volume-title":"IEEE Device Res. Conf","author":"M Luisier","year":"2009","unstructured":"Luisier, M. & Klimeck, G. Performance limitations of graphene nano ribbon tunneling FETS due to line edge roughness. IEEE Device Res. Conf. 201\u2013202 (IEEE, 2009)."},{"key":"BFnature10679_CR75","doi-asserted-by":"publisher","first-page":"1096","DOI":"10.1109\/LED.2009.2028248","volume":"30","author":"G Fiori","year":"2009","unstructured":"Fiori, G. & Iannaccone, G. Ultralow-voltage bilayer graphene tunnel FET. IEEE Electron Device Lett. 30, 1096\u20131098 (2009).","journal-title":"IEEE Electron Device Lett."},{"key":"BFnature10679_CR76","unstructured":"ITRS International Technology Working Groups. International Technology Roadmap for Semiconductors \u3008\n                    http:\/\/www.itrs.net\n                    \n                  \u3009 (2010)."},{"key":"BFnature10679_CR77","doi-asserted-by":"publisher","first-page":"1102","DOI":"10.1109\/LED.2009.2028907","volume":"30","author":"S Mookerjea","year":"2009","unstructured":"Mookerjea, S., Krishnan, R., Datta, S. & Narayanan, V. On enhanced Miller capacitance effect in interband tunnel transistors. IEEE Electron Device Lett. 30, 1102\u20131104 (2009).","journal-title":"IEEE Electron Device Lett."},{"key":"BFnature10679_CR78","doi-asserted-by":"publisher","first-page":"456","DOI":"10.1109\/TED.2008.2011934","volume":"56","author":"S Koswatta","year":"2009","unstructured":"Koswatta, S., Lundstrom, M. & Nikonov, D. Performance comparison between p-i-n tunneling transistors and conventional MOSFETs. IEEE Trans. Electron Devices 56, 456\u2013465 (2009).","journal-title":"IEEE Trans. Electron Devices"},{"key":"BFnature10679_CR79","doi-asserted-by":"publisher","first-page":"197","DOI":"10.1109\/DRC.2011.5994495","volume-title":"IEEE Device Res. Conf","author":"PM Solomon","year":"2011","unstructured":"Solomon, P. M., Frank, D. J. & Koswatta, S. O. Compact model and performance estimation for tunneling nanowire FET. IEEE Device Res. Conf. 197\u2013198 (IEEE, 2011)."},{"key":"BFnature10679_CR80","first-page":"124","volume-title":"Proc. 25th Int. Conf. Microelectron","author":"M Born","year":"2006","unstructured":"Born, M. et al. Tunnel FET: a CMOS device for high temperature applications. Proc. 25th Int. Conf. Microelectron. 124\u2013127 (IEEE, 2006)."},{"key":"BFnature10679_CR81","first-page":"579","volume-title":"Proc. INEC","author":"M Fulde","year":"2008","unstructured":"Fulde, M. et al. Fabrication, optimization, and application of complementary multiple-gate tunneling FETs. Proc. INEC 579\u2013584 (IEEE, 2008)."},{"key":"BFnature10679_CR82","doi-asserted-by":"publisher","first-page":"181","DOI":"10.1016\/0022-3697(60)90035-4","volume":"12","author":"EO Kane","year":"1959","unstructured":"Kane, E. O. Zener tunneling in semiconductors. J. Phys. Chem. Solids 12, 181\u2013188 (1959).","journal-title":"J. Phys. Chem. Solids"},{"key":"BFnature10679_CR83","doi-asserted-by":"publisher","first-page":"564","DOI":"10.1109\/LED.2010.2045631","volume":"31","author":"S Mookerjea","year":"2010","unstructured":"Mookerjea, S., Mohata, D., Mayer, T., Narayanan, V. & Datta, S. Temperature-dependent I\u2013V characteristics of a vertical In0.53Ga0.47As tunnel FET. IEEE Electron Device Lett. 31, 564\u2013566 (2010).","journal-title":"IEEE Electron Device Lett."},{"key":"BFnature10679_CR84","doi-asserted-by":"publisher","first-page":"2911","DOI":"10.1109\/TED.2011.2159797","volume":"58","author":"KE Moselund","year":"2011","unstructured":"Moselund, K. E. et al. Silicon nanowire tunnel FETs: low-temperature operation and influence of high-k gate dielectric. IEEE Trans. Electron Devices 58, 2911\u20132916 (2011).","journal-title":"IEEE Trans. Electron Devices"},{"key":"BFnature10679_CR85","first-page":"181","volume-title":"Proc. Asia S. Pacif. Design Automat. Conf","author":"J Singh","year":"2010","unstructured":"Singh, J. et al. A novel Si-tunnel FET based SRAM design for ultra low-power 0.3 V V DD applications. Proc. Asia S. Pacif. Design Automat. Conf. 181\u2013186 (ACM, 2010)."},{"key":"BFnature10679_CR86","doi-asserted-by":"publisher","first-page":"101","DOI":"10.1109\/DRC.2010.5551859","volume-title":"IEEE Device Res. Conf","author":"V Saripalli","year":"2010","unstructured":"Saripalli, V., Mohata, D. K., Mookerjea, S., Datta, S. & Narayanan, V. Low power loadless 4T SRAM cell based on degenerately doped source (DDS) In0.53Ga0.47As tunnel FETs. IEEE Device Res. Conf. 101\u2013102 (IEEE, 2010)."}],"container-title":["Nature"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/www.nature.com\/articles\/nature10679.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/www.nature.com\/articles\/nature10679","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/www.nature.com\/articles\/nature10679.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,5,18]],"date-time":"2023-05-18T17:56:59Z","timestamp":1684432619000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.nature.com\/articles\/nature10679"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,11]]},"references-count":86,"journal-issue":{"issue":"7373","published-print":{"date-parts":[[2011,11]]}},"alternative-id":["BFnature10679"],"URL":"https:\/\/doi.org\/10.1038\/nature10679","relation":{},"ISSN":["0028-0836","1476-4687"],"issn-type":[{"value":"0028-0836","type":"print"},{"value":"1476-4687","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,11]]}}}