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This trend is receiving more attention lately due to the increasing frequency and sophistication of cyber threats to Internet of Things (IoT) networks. This paper proposes a novel cryptographic co-processor architecture based on RISC-V, designed to offer both high efficiency and flexibility for IoT applications. The design introduces a generic interface for cipher blocks, supports parallel execution of cipher operations, and avoids custom modifications to the RISC-V instruction set architecture. The proposed design extends the RISC-V architecture without new instruction sets to support AES-128 and SHA-256 operations, demonstrating its capabilities through these ciphering blocks. The new processor architecture ensures efficient data transfers between memory and cipher units, without delaying the processor pipeline, by utilizing Memory-Mapped I\/O (MMIO) and Direct Memory Access (DMA) modules to optimize data handling. The proposed design is implemented and verified on the Xilinx ZCU-102 FPGA board using the Vivado 2022.2 tool. The proposed design achieves throughput rates of 8.2 Gbps for the AES-128 cipher block and 482 Mbps for the SHA-256 cipher block, operating at a relatively low system clock frequency of 64 MHz. The throughput is calculated based on the core cycle count of each algorithm, as this metric is commonly adopted in the literature. Nevertheless, the total end-to-end cycles of the proposed design equal the core cycles plus the serializer and deserializer cycles. The cycle count of the serializer\/deserializer depends only on the processor\u2019s data bus width. Also, the total power consumption of the proposed design is 1.575 watts. Achieving such high throughput at this reduced frequency is significant as it helps designers better minimize the power consumption, thereby enhancing the overall energy efficiency and performance of the system.<\/jats:p>","DOI":"10.1038\/s41598-026-58079-9","type":"journal-article","created":{"date-parts":[[2026,6,21]],"date-time":"2026-06-21T18:44:47Z","timestamp":1782067487000},"update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A scalable security co-processor design for IoT applications"],"prefix":"10.1038","volume":"16","author":[{"given":"Mohamed","family":"Niazy","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Haytham","family":"Azmi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mervat M. 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