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The hierarchical design allows the synthesis tool to map the functionality with that of standard cells employed through the regular ASIC synthesis flow. For conventional functions, the hierarchical design is structured and then supplied to the synthesis flow, whereas, for unconventional functions, the same method is not reliable, since the current synthesis method does not offer any design\u2010space exploration scheme to arrive at an easy\u2010to\u2010realize design entity. The unconventional functions either take a long synthesis run\u2010time or additional efforts are spent in restructuring the hierarchical design for the desired function to synthesizable ones. Cartesian genetic programing (CGP) allows to not only incorporate custom logic gates for synthesizing the hierarchical design but also aids in the design\u2010space exploration for the targeted function through the custom gates. The CGP configuration evolves difficult\u2010to\u2010realize complex functions with multiple solutions, and filtering through desired Pareto\u2010optimal requirements offers a unique hierarchical design. Incorporating CGP\u2010derived hierarchical designs into the traditional synthesis flow is instrumental for implementing and evaluating higher\u2010order designs comprising nonlinear functional constructs. Six activation functions and power functions that fall in the category of unconventional functions are realized by the CGP method using custom cells to demonstrate the capability. Further, the hierarchical design of these unconventional functions is flattened and compared with the same function that is directly synthesized using basic gates. The CGP\u2010derived synthesis method reports 3\u00d7 less synthesis time for realizing the complex functions at the hierarchical level compared to the synthesis using basic gate cells. Hardware characteristics and error metrics are also investigated for the CGP realized complex functions and are made freely available for further usage to the research and designers\u2019 community.<\/jats:p>","DOI":"10.1049\/2024\/6623637","type":"journal-article","created":{"date-parts":[[2024,1,29]],"date-time":"2024-01-29T16:50:10Z","timestamp":1706547010000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP"],"prefix":"10.1049","volume":"2024","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9650-3731","authenticated-orcid":false,"given":"H. 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