{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,14]],"date-time":"2026-04-14T16:13:24Z","timestamp":1776183204999,"version":"3.50.1"},"reference-count":32,"publisher":"Institution of Engineering and Technology (IET)","issue":"1","license":[{"start":{"date-parts":[[2024,7,2]],"date-time":"2024-07-02T00:00:00Z","timestamp":1719878400000},"content-version":"vor","delay-in-days":183,"URL":"http:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["ietresearch.onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["IET Circuits, Devices &amp; Systems"],"published-print":{"date-parts":[[2024,1]]},"abstract":"<jats:p>This study explores the impact of integrating a gallium arsenide (GaAs) pocket at the source and drain in a dual\u2010material gate\u2010oxide\u2010stack double\u2010gate tunnel field\u2010effect transistor (DMGOSDG\u2010TFET). The performance of this DMGOSDG\u2010TFET, employing work\u2010function engineering and gate\u2010oxide\u2010stack techniques, is compared with a GaAs pocket\u2010doped DMGOSDG\u2010TFET. Using the Silvaco Technology Computer\u2010Aided Design tool, the comparison covers DC characteristics, analog\/RF behavior, and circuit\u2010level assessments. The research introduces an optimized heterostructure pocket\u2010doped DMGOSDG\u2010TFET to enhance DC characteristics, analog\/RF performance, and DC\/transient analysis. This novel architecture effectively suppresses ambipolarity, making it more suitable for current conduction. The incorporation of work\u2010function engineering and a gate\u2010oxide\u2010stack approach enhances the device\u2019s current driving capability, while the use of a highly doped GaAs pocket at the source and drain virtually eliminates ambipolar current conduction. Simulation results indicate that the proposed heterostructure device exhibits a high ON\u2010current and switching ratio. For analog\/RF applications, the optimized heterostructure device outperforms conventional DMGOSDG\u2010TFET, offering higher cutoff frequency, transconductance, and other analog\/RF parameters. Circuit\u2010level performance is assessed using HSPICE, with a focus on the implementation of a resistive\u2010load inverter for both proposed and conventional device topologies through DC and transient evaluations.<\/jats:p>","DOI":"10.1049\/2024\/9925894","type":"journal-article","created":{"date-parts":[[2024,7,2]],"date-time":"2024-07-02T14:19:55Z","timestamp":1719929995000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Performance Assessment of GaAs Pocket\u2010Doped Dual\u2010Material Gate\u2010Oxide\u2010Stack DG\u2010TFET at Device and Circuit Level"],"prefix":"10.1049","volume":"2024","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0093-4535","authenticated-orcid":false,"given":"Km. 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