{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,20]],"date-time":"2026-05-20T19:29:26Z","timestamp":1779305366112,"version":"3.51.4"},"reference-count":25,"publisher":"Institution of Engineering and Technology (IET)","issue":"1","license":[{"start":{"date-parts":[[2026,2,17]],"date-time":"2026-02-17T00:00:00Z","timestamp":1771286400000},"content-version":"vor","delay-in-days":47,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"},{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/doi.wiley.com\/10.1002\/tdm_license_1.1"}],"content-domain":{"domain":["ietresearch.onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["IET Circuits, Devices &amp;amp; Systems"],"published-print":{"date-parts":[[2026,1]]},"abstract":"<jats:p>This work introduces a novel method to improve hardware debugging efficiency and decrease computing time by employing a finite state machine (FSM)\u2010based reconfigurable buffer insertion strategy for optimizing field\u2010programmable gate array (FPGA) performance. The proposed strategy greatly enhances the debugging process by offering a systematic approach for error discovery, so ensuring that the FPGA functions with diminished complexity and increased dependability. Additionally, a reconfigurable decision tree generation (DTG)\u2010finite impulse response (FIR) filter design is shown to optimize circuit area, resulting in a decrease in the quantity of stored memory look\u2010up tables (LUTs). The substantial enhancement in power efficiency and area attained by using 4 LUTs in place of 6 LUTs. This work executes and verifies the register\u2010transfer level (RTL) functionality by operating with 16 taps. This idea depends on the usage of an FSM controller for the utilization of a common buffer. This buffer eliminates the usage of 16 distinct buffers by sharing all 16 taps in order to identify errors. With this approach, the simplified design and overall efficiency are improved. This approach achieves improved debug capabilities with a single common buffer by eliminating usage of multiple buffers. The hardware complexity of the circuit is decreased substantially by using this proposed model. This model proves that the suggested FSM\u2010based buffer insertion and reconfigurable FIR filter design improve computational efficiency and FPGA area optimization, positioning it as a viable alternative for forthcoming FPGA\u2010based designs.<\/jats:p>","DOI":"10.1049\/cds2\/5545245","type":"journal-article","created":{"date-parts":[[2026,2,17]],"date-time":"2026-02-17T09:10:41Z","timestamp":1771319441000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["An FSM\u2010Enabled Reconfigurable Debugging Approach for Area\u2010Optimized FIR Filters on FPGA Platforms"],"prefix":"10.1049","volume":"2026","author":[{"given":"Murali","family":"Anumothu","sequence":"first","affiliation":[]},{"given":"G. M. Anitha","family":"Priyadarshini","sequence":"additional","affiliation":[]},{"given":"Ch. Hima","family":"Bindu","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8508-6066","authenticated-orcid":false,"given":"Rajanikanth","family":"Aluvalu","sequence":"additional","affiliation":[]},{"given":"Sai Prashanth","family":"Mallellu","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8123-3209","authenticated-orcid":false,"given":"Pankaj","family":"Kumar","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9106-0313","authenticated-orcid":false,"given":"Ghanshyam G.","family":"Tejani","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8661-7578","authenticated-orcid":false,"given":"Seyed Jalaleddin","family":"Mousavirad","sequence":"additional","affiliation":[]}],"member":"265","published-online":{"date-parts":[[2026,2,17]]},"reference":[{"key":"e_1_2_11_1_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2095892"},{"key":"e_1_2_11_2_2","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-012-9096-8"},{"key":"e_1_2_11_3_2","volume-title":"Advances in Systems Science","author":"Daoud L.","year":"2014"},{"key":"e_1_2_11_4_2","doi-asserted-by":"crossref","unstructured":"WakabayashiK. CyberWorkBench: Integrated Design Environment Based on C-Based Behavior Synthesis and Verification VLSI-TSA International Symposium on VLSI Design Automation and Test 2005 Hsinchu Taiwan IEEE 173\u2013176.","DOI":"10.1109\/VDAT.2005.1500048"},{"key":"e_1_2_11_5_2","first-page":"3468","article-title":"An Efficient Debugging Architecture for DTG Based FIR Filter Using I. 2 C Protocol in DSP Processor","volume":"8","author":"Murali A.","year":"2020","journal-title":"International Journal of Emerging Trends in Engineering Research"},{"key":"e_1_2_11_6_2","doi-asserted-by":"publisher","DOI":"10.1007\/s10772-020-09784-x"},{"key":"e_1_2_11_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2024.3504008"},{"key":"e_1_2_11_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2587105"},{"key":"e_1_2_11_9_2","first-page":"1588","article-title":"A New Cost Aware Sensitivity-Driven Algorithm for the Design of FIR Filters","volume":"64","author":"Chen J.","year":"2017","journal-title":"IEEE Transactions on Circuits and Systems I: Regular Papers"},{"key":"e_1_2_11_10_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2412556"},{"key":"e_1_2_11_11_2","doi-asserted-by":"publisher","DOI":"10.1109\/43.486662"},{"key":"e_1_2_11_12_2","first-page":"176","article-title":"Multiple Constant Multiplication Algorithm for High Speed and Low Power Design","volume":"63","author":"Oudjida A. K.","year":"2015","journal-title":"IEEE Transactions on Circuits and Systems II: Express Briefs"},{"key":"e_1_2_11_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/82.466647"},{"key":"e_1_2_11_14_2","first-page":"559","article-title":"Contention Resolution\u2014A New Approach to Versatile Sub Expressions Sharing in Multiple Constant Multiplications","volume":"55","author":"Xu F.","year":"2008","journal-title":"IEEE Transactions on Circuits and Systems I: Regular Papers"},{"key":"e_1_2_11_15_2","first-page":"196","article-title":"Design of High-Speed Multiplier less Filters Using a No Recursive Signed Common Sub Expression Algorithm","volume":"49","author":"Peiro M. M.","year":"2002","journal-title":"IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing"},{"key":"e_1_2_11_16_2","first-page":"2310","article-title":"Information Theoretic Approach to Complexity Reduction of FIR Filter Design","volume":"55","author":"Chang C. H.","year":"2008","journal-title":"IEEE Transactions on Circuits and Systems I: Regular Papers"},{"key":"e_1_2_11_17_2","first-page":"707","article-title":"An RNS Based FIR Filter Design Using Shift and Add Approach","author":"Kotha S. R.","year":"2014","journal-title":"Midwest Symposium on Circuits and Systems"},{"key":"e_1_2_11_18_2","doi-asserted-by":"crossref","unstructured":"JohanssonK. GustafssonO. andWanhammarL. Bit-Level Optimization of Shift-and-Add Based FIR Filters 2007 14th IEEE International Conference on Electronics Circuits and Systems 2007 Marrakech Morocco IEEE 713\u2013716 https:\/\/doi.org\/10.1109\/ICECS.2007.4511091 2-s2.0-50649110937.","DOI":"10.1109\/ICECS.2007.4511091"},{"key":"e_1_2_11_19_2","doi-asserted-by":"crossref","first-page":"4247","DOI":"10.1109\/TCSI.2018.2838666","article-title":"Efficient Shiftadd Implementation of FIR Filters Using Variable Partition Hybrid Form Structures","volume":"65","author":"Dwaipayan R.","year":"2018","journal-title":"IEEE Transactions on Circuits and Systems-I, Regular Works"},{"key":"e_1_2_11_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.854631"},{"key":"e_1_2_11_21_2","doi-asserted-by":"crossref","first-page":"1591","DOI":"10.1109\/TCAD.2015.2513673","article-title":"A Survey and Evaluation of FPGA High-Level Synthesis Tools\u201d","volume":"35","author":"Nane R.","year":"2016","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_2_11_22_2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2399275"},{"key":"e_1_2_11_23_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2110592"},{"key":"e_1_2_11_24_2","doi-asserted-by":"publisher","DOI":"10.35940\/ijitee.C8448.019320"},{"key":"e_1_2_11_25_2","volume-title":"Digital Signal Processing: Principles, Algorithms and Applications","author":"Proakis J. G.","year":"1996"}],"container-title":["IET Circuits, Devices &amp; Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/ietresearch.onlinelibrary.wiley.com\/doi\/pdf\/10.1049\/cds2\/5545245","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/ietresearch.onlinelibrary.wiley.com\/doi\/full-xml\/10.1049\/cds2\/5545245","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/ietresearch.onlinelibrary.wiley.com\/doi\/pdf\/10.1049\/cds2\/5545245","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,17]],"date-time":"2026-02-17T09:10:43Z","timestamp":1771319443000},"score":1,"resource":{"primary":{"URL":"https:\/\/ietresearch.onlinelibrary.wiley.com\/doi\/10.1049\/cds2\/5545245"}},"subtitle":[],"editor":[{"given":"NandhaKumar","family":"Thulasiraman","sequence":"additional","affiliation":[]}],"short-title":[],"issued":{"date-parts":[[2026,1]]},"references-count":25,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2026,1]]}},"alternative-id":["10.1049\/cds2\/5545245"],"URL":"https:\/\/doi.org\/10.1049\/cds2\/5545245","archive":["Portico"],"relation":{},"ISSN":["1751-858X","1751-8598"],"issn-type":[{"value":"1751-858X","type":"print"},{"value":"1751-8598","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,1]]},"assertion":[{"value":"2025-09-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-12-16","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2026-02-17","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}],"article-number":"5545245"}}