{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,11,13]],"date-time":"2024-11-13T05:28:51Z","timestamp":1731475731933,"version":"3.28.0"},"reference-count":18,"publisher":"Institution of Engineering and Technology (IET)","issue":"1","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IET Comput. Digit. Tech."],"published-print":{"date-parts":[[2007,1,9]]},"DOI":"10.1049\/iet-cdt:20060016","type":"journal-article","created":{"date-parts":[[2007,2,15]],"date-time":"2007-02-15T16:28:12Z","timestamp":1171556892000},"page":"17-26","source":"Crossref","is-referenced-by-count":0,"title":["ROM to DSP block transfer for resource constrained synthesis"],"prefix":"10.1049","volume":"1","author":[{"given":"G.W.","family":"Morris","sequence":"first","affiliation":[{"name":"Circuits and Systems Group, Department of Electronic and Electrical Engineering, Imperial College, Exhibition Road, London, SW7 2BT, UK"}]},{"given":"G.A.","family":"Constantinides","sequence":"additional","affiliation":[{"name":"Circuits and Systems Group, Department of Electronic and Electrical Engineering, Imperial College, Exhibition Road, London, SW7 2BT, UK"}]},{"given":"P.Y.K.","family":"Cheung","sequence":"additional","affiliation":[{"name":"Circuits and Systems Group, Department of Electronic and Electrical Engineering, Imperial College, Exhibition Road, London, SW7 2BT, UK"}]}],"member":"265","reference":[{"key":"10.1049\/iet-cdt:20060016_r1","doi-asserted-by":"crossref","unstructured":"Hutton, M., Scleicher, J., Lewis, D., Pedersen, B., Ynan, R., and Kaptanoglu, S.: \u2018Improving FPGA performance and area using an adaptable logic module\u2019, Becker, J., Platzner, M., Vernalde, S., Proceedings of the Field programmable logic, (Springer LNCS 2004)","DOI":"10.1007\/978-3-540-30117-2_16"},{"journal-title":"Proc. IEEE Int. Conf. on Field-Programmable Technology","year":"2002","author":"Wilton","key":"10.1049\/iet-cdt:20060016_r2"},{"key":"10.1049\/iet-cdt:20060016_r3","unstructured":"Murgai, R.: \u2018Logic synthesis for field-programmable gate arrays\u2019, 1993, PhD, University of California at Berkeley Thesis"},{"key":"10.1049\/iet-cdt:20060016_r4","unstructured":"Xilinx CORE Generator Guide Xilinx 1994\u20132002"},{"key":"10.1049\/iet-cdt:20060016_r5","doi-asserted-by":"publisher","DOI":"10.1109\/54.632877"},{"journal-title":"Proc. 12th IEEE Symp. on Comp. Arith.","year":"1995","author":"DasSarma","key":"10.1049\/iet-cdt:20060016_r6"},{"journal-title":"Proc. 13th IEEE Symp. on Comp. Arith.","year":"1997","author":"Schulte","key":"10.1049\/iet-cdt:20060016_r7"},{"key":"10.1049\/iet-cdt:20060016_r8","first-page":"118","volume":"37","author":"Andrews","year":"2004"},{"key":"10.1049\/iet-cdt:20060016_r9","doi-asserted-by":"crossref","first-page":"61","DOI":"10.1016\/0021-9045(74)90058-6","volume":"12","author":"Pavlidis","year":"1974","ISSN":"http:\/\/id.crossref.org\/issn\/0021-9045","issn-type":"print"},{"key":"10.1049\/iet-cdt:20060016_r10","doi-asserted-by":"publisher","DOI":"10.1023\/A:1009984523264"},{"journal-title":"Proc. 15th IEEE Symp. on Comp. Arith.","year":"2001","author":"de Dinechin","key":"10.1049\/iet-cdt:20060016_r11"},{"journal-title":"Proc. 36th Conf. on Signals Syst. Comput.","year":"2002","author":"Defour","key":"10.1049\/iet-cdt:20060016_r12"},{"journal-title":"Proc. Field Programmable Logic","year":"2005","author":"Morris","key":"10.1049\/iet-cdt:20060016_r13"},{"key":"10.1049\/iet-cdt:20060016_r14","doi-asserted-by":"publisher","DOI":"10.1109\/43.822620"},{"journal-title":"Proc. 21st Southeastern Symp. on System Theory","year":"1989","author":"Aravena","key":"10.1049\/iet-cdt:20060016_r15"},{"key":"10.1049\/iet-cdt:20060016_r16","doi-asserted-by":"crossref","first-page":"1087","DOI":"10.1063\/1.1699114","volume":"21","author":"Metropolis","year":"1953","ISSN":"http:\/\/id.crossref.org\/issn\/0021-9606","issn-type":"print"},{"key":"10.1049\/iet-cdt:20060016_r17","unstructured":"\u2018Migrating functionality from ROMs to embedded multipliers\u2019, MPhil\u2215PhD Transfer Report, Imperial College of Science, Technology and Medicine, 2004"},{"key":"10.1049\/iet-cdt:20060016_r18","unstructured":"Altera Corporation, Quartus II University Program (QUIP) Version 2.1, Altera 2004"}],"container-title":["IET Computers & Digital Techniques"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/digital-library.theiet.org\/content\/journals\/10.1049\/iet-cdt_20060016?crawler=true&mimetype=application\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,11,12]],"date-time":"2024-11-12T15:05:26Z","timestamp":1731423926000},"score":1,"resource":{"primary":{"URL":"http:\/\/digital-library.theiet.org\/doi\/10.1049\/iet-cdt%3A20060016"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,1,9]]},"references-count":18,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2007,1,9]]}},"alternative-id":["10.1049\/iet-cdt:20060016"],"URL":"https:\/\/doi.org\/10.1049\/iet-cdt:20060016","relation":{},"ISSN":["1751-8601","1751-861X"],"issn-type":[{"type":"print","value":"1751-8601"},{"type":"electronic","value":"1751-861X"}],"subject":[],"published":{"date-parts":[[2007,1,9]]}}}