{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,24]],"date-time":"2025-12-24T12:13:53Z","timestamp":1766578433609,"version":"3.33.0"},"reference-count":20,"publisher":"Institution of Engineering and Technology (IET)","issue":"3","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IET Comput. Digit. Tech."],"published-print":{"date-parts":[[2007,5]]},"DOI":"10.1049\/iet-cdt:20060137","type":"journal-article","created":{"date-parts":[[2007,5,11]],"date-time":"2007-05-11T16:23:22Z","timestamp":1178900602000},"page":"237-245","source":"Crossref","is-referenced-by-count":18,"title":["March AB, a state-of-the-art march test for realistic static linked faults and dynamic faults in SRAMs"],"prefix":"10.1049","volume":"1","author":[{"given":"A.","family":"Bosio","sequence":"first","affiliation":[{"name":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Corso Duca degli Abruzzi 24, Torino, I-10129, Italy"}]},{"given":"S.","family":"Di Carlo","sequence":"additional","affiliation":[{"name":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Corso Duca degli Abruzzi 24, Torino, I-10129, Italy"}]},{"given":"G.","family":"Di Natale","sequence":"additional","affiliation":[{"name":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Corso Duca degli Abruzzi 24, Torino, I-10129, Italy"}]},{"given":"P.","family":"Prinetto","sequence":"additional","affiliation":[{"name":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Corso Duca degli Abruzzi 24, Torino, I-10129, Italy"}]}],"member":"265","reference":[{"key":"10.1049\/iet-cdt:20060137_r1","doi-asserted-by":"crossref","unstructured":"Marinissen, E.J., Prince, B., Keltel-Schulz, D., and Zorian, Y.: \u2018Challenges in embedded memory design and test\u2019, Design, Automation and Test in Europe, Munich, Germany 2005 March),2, p. 722\u2013727","DOI":"10.1109\/DATE.2005.92"},{"key":"10.1049\/iet-cdt:20060137_r2","unstructured":"Van de Goor, A.J.: \u2018Testing semiconductor memories: theory and practice\u2019, (Wiley, Chichester, UK 1991)"},{"key":"10.1049\/iet-cdt:20060137_r3","doi-asserted-by":"crossref","unstructured":"Hamdioui, S., Wadsworth, R., Reyes, J.D., and Van de Goor, A.J.: \u2018Importance of dynamic faults for new SRAM technologies\u2019, 8th IEEE European Test Workshop, Maastricht, The Netherlands 2003 May), p. 29\u201334","DOI":"10.1109\/ETW.2003.1231665"},{"key":"10.1049\/iet-cdt:20060137_r4","doi-asserted-by":"crossref","unstructured":"Al-Ars, Z., and Van de Goor, A.J.: \u2018Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs\u2019, IEEE Design Automation and Test in Europe, Munich, Germany 2001 March), p. 496\u2013503","DOI":"10.1109\/DATE.2001.915069"},{"key":"10.1049\/iet-cdt:20060137_r5","doi-asserted-by":"crossref","unstructured":"Van de Goor, A.J., and Al-Ars, Z.: \u2018Functional memory faults: a formal notation and a taxonomy\u2019, 18th IEEE VLSI Test Symp., Marina Del Rey, CA, USA 2000 May), p. 281\u2013289","DOI":"10.1109\/VTEST.2000.843856"},{"key":"10.1049\/iet-cdt:20060137_r6","doi-asserted-by":"crossref","unstructured":"Al-Ars, Z., and Van de Goor, A.J.: \u2018Approximating infinite dynamic behavior for DRAM cell defects\u2019, 20th IEEE VLSI Test Symp., Monterey, CA, USA 2002 May), p. 401\u2013406","DOI":"10.1109\/VTS.2002.1011171"},{"key":"10.1049\/iet-cdt:20060137_r7","doi-asserted-by":"crossref","first-page":"567","DOI":"10.1109\/43.55188","volume":"9","author":"Dekker","year":"1990","ISSN":"https:\/\/id.crossref.org\/issn\/0278-0070","issn-type":"print"},{"key":"10.1049\/iet-cdt:20060137_r8","doi-asserted-by":"crossref","unstructured":"Hamdioui, S., Van de Goor, A.J., and Rodgers, M.: \u2018March SS: a test for all static simple RAM faults\u2019, IEEE Int. Workshop on Memory Technology, Design and Testing, Isle the Bendor, France 2002 July), p. 95\u2013100","DOI":"10.1109\/MTDT.2002.1029769"},{"key":"10.1049\/iet-cdt:20060137_r9","first-page":"236","author":"Marinescu","year":"1982","journal-title":"IEEE Int. Test Conf."},{"key":"10.1049\/iet-cdt:20060137_r10","doi-asserted-by":"crossref","first-page":"982","DOI":"10.1109\/TC.1981.1675739","volume":"30","author":"Suk","year":"1981","ISSN":"https:\/\/id.crossref.org\/issn\/0018-9340","issn-type":"print"},{"key":"10.1049\/iet-cdt:20060137_r11","doi-asserted-by":"crossref","unstructured":"Hamdioui, S., Al-Ars, Z., and Van de Goor, A.J.: \u2018Testing static and dynamic faults in random access memories\u2019, 20th IEEE VLSI Test Symp., Monterey, CA, USA 2002 May), p. 395\u2013400","DOI":"10.1109\/VTS.2002.1011170"},{"key":"10.1049\/iet-cdt:20060137_r12","doi-asserted-by":"crossref","unstructured":"Dilillo, L., Girard, P., Pravossoudovitch, S., Virazel, A., Borri, S., and Hage-Hassan, M.: \u2018Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution\u2019, 9th IEEE European Test Symp., Ajaccio, Corsica, France 2004 May), p. 140\u2013145","DOI":"10.1109\/ETSYM.2004.1347645"},{"key":"10.1049\/iet-cdt:20060137_r13","first-page":"167","author":"Van de Goor","year":"1997","journal-title":"European Design and Test Conf."},{"key":"10.1049\/iet-cdt:20060137_r14","doi-asserted-by":"crossref","unstructured":"Van de Goor, A.J., Gayadadjiev, G.N., Yarmolik, V.N., and Mikitjuk, V.G.: \u2018March LR: a test for realistic linked faults\u2019, 16th IEEE VLSI Test Symp., Princeton, NJ, USA 1996 May), p. 272\u2013280","DOI":"10.1109\/VTEST.1996.510868"},{"key":"10.1049\/iet-cdt:20060137_r15","doi-asserted-by":"crossref","unstructured":"Al-Harbi, S.M., and Gupta, S.K.: \u2018Generating complete and optimal march tests for linked faults in memories\u2019, IEEE VLSI Test Symp., Napa Valley, CA, USA 2003 April), p. 254\u2013261","DOI":"10.1109\/VTEST.2003.1197659"},{"key":"10.1049\/iet-cdt:20060137_r16","first-page":"372","author":"Hamdioui","year":"2003","journal-title":"IEEE Asian Test Symp."},{"key":"10.1049\/iet-cdt:20060137_r17","doi-asserted-by":"crossref","first-page":"737","DOI":"10.1109\/TCAD.2004.826578","volume":"23","author":"Hamdioui","year":"2004","ISSN":"https:\/\/id.crossref.org\/issn\/0278-0070","issn-type":"print"},{"key":"10.1049\/iet-cdt:20060137_r18","doi-asserted-by":"crossref","first-page":"120","DOI":"10.1109\/VTS.2006.46","author":"Harutunyan","year":"2006","journal-title":"IEEE VLSI Test Symp."},{"key":"10.1049\/iet-cdt:20060137_r19","doi-asserted-by":"crossref","first-page":"122","DOI":"10.1109\/ETS.2005.8","author":"Benso","year":"2005","journal-title":"IEEE European Test Symp."},{"key":"10.1049\/iet-cdt:20060137_r20","first-page":"92","author":"Benso","year":"2002","journal-title":"IEEE Asian Test Symp."}],"container-title":["IET Computers &amp; Digital Techniques"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/digital-library.theiet.org\/content\/journals\/10.1049\/iet-cdt_20060137?crawler=true&mimetype=application\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,16]],"date-time":"2025-01-16T05:40:30Z","timestamp":1737006030000},"score":1,"resource":{"primary":{"URL":"http:\/\/digital-library.theiet.org\/doi\/10.1049\/iet-cdt%3A20060137"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,5]]},"references-count":20,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2007,5]]}},"alternative-id":["10.1049\/iet-cdt:20060137"],"URL":"https:\/\/doi.org\/10.1049\/iet-cdt:20060137","relation":{},"ISSN":["1751-8601","1751-861X"],"issn-type":[{"type":"print","value":"1751-8601"},{"type":"electronic","value":"1751-861X"}],"subject":[],"published":{"date-parts":[[2007,5]]}}}