{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,13]],"date-time":"2026-03-13T12:55:22Z","timestamp":1773406522205,"version":"3.50.1"},"reference-count":13,"publisher":"Institution of Engineering and Technology (IET)","issue":"1","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IET Comput. Digit. Tech."],"published-print":{"date-parts":[[2008,1,9]]},"DOI":"10.1049\/iet-cdt:20070040","type":"journal-article","created":{"date-parts":[[2008,1,12]],"date-time":"2008-01-12T23:46:37Z","timestamp":1200181597000},"page":"40-44","source":"Crossref","is-referenced-by-count":9,"title":["Critical race-free low-power NAND match line content addressable memory tagged cache memory"],"prefix":"10.1049","volume":"2","author":[{"given":"V.","family":"Chaudhary","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, Arizona State University, PO Box 875706, Tempe, AZ 85287, USA"}]},{"given":"T.-H.","family":"Chen","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Arizona State University, PO Box 875706, Tempe, AZ 85287, USA"}]},{"given":"F.","family":"Sheerin","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Arizona State University, PO Box 875706, Tempe, AZ 85287, USA"}]},{"given":"L.T.","family":"Clark","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Arizona State University, PO Box 875706, Tempe, AZ 85287, USA"}]}],"member":"265","reference":[{"key":"10.1049\/iet-cdt:20070040_r1","unstructured":"Furber, S.: \u2018ARM system architecture\u2019, (Addison-Wesley, MA, USA 1996)"},{"key":"10.1049\/iet-cdt:20070040_r2","doi-asserted-by":"crossref","first-page":"288","DOI":"10.1109\/4.962279","volume":"36","author":"Clark","year":"2001","ISSN":"https:\/\/id.crossref.org\/issn\/0018-9200","issn-type":"print"},{"key":"10.1049\/iet-cdt:20070040_r3","doi-asserted-by":"crossref","first-page":"52","DOI":"10.1109\/2.917539","volume":"34","author":"Mudge","year":"2001","ISSN":"https:\/\/id.crossref.org\/issn\/0018-9162","issn-type":"print"},{"key":"10.1049\/iet-cdt:20070040_r4","first-page":"926","author":"Hsiao","year":"2001","journal-title":"Proc. IEEE Int. Symp. on Circuits and Systems"},{"key":"10.1049\/iet-cdt:20070040_r5","unstructured":"Weste, N., and Harris, D.: \u2018CMOS VLSI design: a circuit and systems perspective\u2019, 3rd(Addison-Wesley, MA, USA 2005)"},{"key":"10.1049\/iet-cdt:20070040_r6","doi-asserted-by":"crossref","first-page":"633","DOI":"10.1109\/4.997857","volume":"37","author":"Alvandpour","year":"2002","ISSN":"https:\/\/id.crossref.org\/issn\/0018-9200","issn-type":"print"},{"key":"10.1049\/iet-cdt:20070040_r7","doi-asserted-by":"crossref","first-page":"1210","DOI":"10.1109\/4.705359","volume":"33","author":"Amrutur","year":"1998","ISSN":"https:\/\/id.crossref.org\/issn\/0018-9200","issn-type":"print"},{"key":"10.1049\/iet-cdt:20070040_r8","doi-asserted-by":"crossref","first-page":"91","DOI":"10.1109\/92.994983","volume":"10","author":"Hamzaoglu","year":"2002","ISSN":"https:\/\/id.crossref.org\/issn\/1063-8210","issn-type":"print"},{"key":"10.1049\/iet-cdt:20070040_r9","doi-asserted-by":"crossref","first-page":"325","DOI":"10.1109\/TVLSI.2004.824298","volume":"12","author":"Efthymiou","year":"2004","ISSN":"https:\/\/id.crossref.org\/issn\/1063-8210","issn-type":"print"},{"key":"10.1049\/iet-cdt:20070040_r10","doi-asserted-by":"crossref","first-page":"895","DOI":"10.1109\/TVLSI.2006.878476","volume":"14","author":"Chaudhary","year":"2006","ISSN":"https:\/\/id.crossref.org\/issn\/1063-8210","issn-type":"print"},{"key":"10.1049\/iet-cdt:20070040_r11","first-page":"394","author":"Cho","year":"2001","journal-title":"Int. Conf. on Computer Design Proc."},{"key":"10.1049\/iet-cdt:20070040_r12","doi-asserted-by":"crossref","first-page":"666","DOI":"10.1109\/4.913745","volume":"36","author":"Perng-Fei","year":"2001","ISSN":"https:\/\/id.crossref.org\/issn\/0018-9200","issn-type":"print"},{"key":"10.1049\/iet-cdt:20070040_r13","unstructured":"\u2018The F1: TI's 65-nm Cortex-A8\u2019, Microprocessor Report, 24, July, 2006 p. 1\u20135"}],"container-title":["IET Computers & Digital Techniques"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/digital-library.theiet.org\/content\/journals\/10.1049\/iet-cdt_20070040?crawler=true&mimetype=application\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,11,12]],"date-time":"2024-11-12T14:31:09Z","timestamp":1731421869000},"score":1,"resource":{"primary":{"URL":"http:\/\/digital-library.theiet.org\/doi\/10.1049\/iet-cdt%3A20070040"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,1,9]]},"references-count":13,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2008,1,9]]}},"alternative-id":["10.1049\/iet-cdt:20070040"],"URL":"https:\/\/doi.org\/10.1049\/iet-cdt:20070040","relation":{},"ISSN":["1751-8601","1751-861X"],"issn-type":[{"value":"1751-8601","type":"print"},{"value":"1751-861X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2008,1,9]]}}}