{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,20]],"date-time":"2026-02-20T18:51:38Z","timestamp":1771613498458,"version":"3.50.1"},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2002,1]]},"abstract":"<jats:p>In this paper, a low\u2010voltage, high performance charge pump circuit, suitable for implementation in standard CMOS technologies is proposed. Its pumping operation is based on cascading several cross\u2010connected NMOS voltage doubler stages. For very low\u2010voltage applications (1.2 V, 0.9 V), where the performance of the NMOS transistors is limited due to body effect, two improved versions of the charge pump with cascaded voltage doublers (charge pump with CVD) are also proposed. The first utilises PMOS transistors (charge pump with CVD\u2010PMOS) in parallel to the cross\u2010connected NMOS transistors, while the second improves the pumping gain by boosting the clock amplitude (charge pump with CVD\u2010BCLK). Simulations at 50 MHz have shown that a five\u2010stages charge pump with CVD can achieve a 1.5\u20138.4 V voltage conversion. For the same stage number and frequency, an output voltage of 4 and 7.3 V can be generated from 0.9 V, by using the charge pump with CVD\u2010PMOS and the charge pump with CVD\u2010BCLK, respectively.<\/jats:p>","DOI":"10.1080\/1065514021000012084","type":"journal-article","created":{"date-parts":[[2002,11,14]],"date-time":"2002-11-14T05:14:22Z","timestamp":1037250862000},"page":"477-483","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":8,"title":["Charge Pump Circuits for Low\u2010voltage Applications"],"prefix":"10.1155","volume":"15","author":[{"given":"Y.","family":"Moisiadis","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"I.","family":"Bouras","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Arapoyanni","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2001,3,26]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2002\/216208.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1080\/1065514021000012084","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T22:35:41Z","timestamp":1723070141000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1080\/1065514021000012084"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001,3,26]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2002,1]]}},"alternative-id":["10.1080\/1065514021000012084"],"URL":"https:\/\/doi.org\/10.1080\/1065514021000012084","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"value":"1065-514X","type":"print"},{"value":"1563-5171","type":"electronic"}],"subject":[],"published":{"date-parts":[[2001,3,26]]},"assertion":[{"value":"2001-02-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2001-03-26","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}