{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T23:40:01Z","timestamp":1723074001296},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2002,1]]},"abstract":"<jats:p>An automatic logic\/circuit synthesizer is developed which takes several Boolean functions as input and generates netlist output with basic composing cells from the pass\u2010transistor cell library containing only two types of cells: 2\u2010to\u20101 multiplexers and inverters. The synthesis procedure first constructs efficient binary decision diagrams (BDDs) for these Boolean functions considering both multi\u2010function sharing and minimum width. Each node in the BDD trees is realized by using a 2\u2010to\u20101 multiplexer (MUX) of proper driving capability designed pass\u2010transistor logic. The inverters are then inserted all along the MUX paths in order to improve the speed performance and to alleviate the voltage\u2010drop problem. Several methods are proposed to reduce the critical path delay in the multiplexer\u2010chains for generation of faster circuits. Compared to the recently proposed pass\u2010transistor\u2010based top\u2010down design, our synthesizer has better speed and area performance due to the reduced number of cascaded inverters.<\/jats:p>","DOI":"10.1080\/1065514021000054736","type":"journal-article","created":{"date-parts":[[2002,11,14]],"date-time":"2002-11-14T05:14:22Z","timestamp":1037250862000},"page":"417-426","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":7,"title":["High\u2010performance Multiplexer\u2010based Logic Synthesis Using Pass\u2010transistor Logic"],"prefix":"10.1155","volume":"15","author":[{"given":"Shen-Fu","family":"Hsiao","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jia-Siang","family":"Yeh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Da-Yen","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2001,3,2]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2002\/471390.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1080\/1065514021000054736","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T22:35:37Z","timestamp":1723070137000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1080\/1065514021000054736"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001,3,2]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2002,1]]}},"alternative-id":["10.1080\/1065514021000054736"],"URL":"https:\/\/doi.org\/10.1080\/1065514021000054736","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[2001,3,2]]},"assertion":[{"value":"2001-02-13","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2001-03-02","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}