{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T18:10:01Z","timestamp":1723140601969},"reference-count":0,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/501100000038","name":"Natural Sciences and Engineering Research Council of Canada","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100000038","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2002,1]]},"abstract":"<jats:p>In this paper, a high\u2010speed parallel residue\u2010to\u2010binary converter is proposed for a recently introduced moduli set   for a general value of <jats:italic>k<\/jats:italic>. The proposed converter uses simple cyclic shift and concatenation operations and does not require any multiplier. Individual converters for the cases of  <jats:italic>k<\/jats:italic> = 0 and <jats:italic>k<\/jats:italic> = 1 are derived from the general architecture and compared with those existing in the literature. The converter for <jats:italic>S<\/jats:italic><jats:sup>0<\/jats:sup> is twice as fast requiring only one\u2010half of the hardware, while that of <jats:italic>S<\/jats:italic><jats:sup>1<\/jats:sup> is three times as fast, but requiring only 60% of the hardware, as compared to the corresponding ones existing in the literature. Furthermore, the proposed converters are implemented using 0.5\u2010micron CMOS VLSI technology. Based on <jats:italic>S<\/jats:italic><jats:sup>0<\/jats:sup> , the layouts for 8\u2010bit, 16\u2010bit, 32\u2010bit and 64\u2010bit converters are generated, and the corresponding simulation results obtained.<\/jats:p>","DOI":"10.1080\/10655140290010097","type":"journal-article","created":{"date-parts":[[2002,8,25]],"date-time":"2002-08-25T09:42:24Z","timestamp":1030268544000},"page":"183-191","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["A Parallel Residue\u2010to\u2010binary Converter for the Moduli Set {2m\u22121111,220m+,221m+,\u2026,22km+}"],"prefix":"10.1155","volume":"14","author":[{"given":"Wei","family":"Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M. N. S.","family":"Swamy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M. O.","family":"Ahmad","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuke","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2000,3,9]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2002\/512468.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1080\/10655140290010097","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T16:58:22Z","timestamp":1723136302000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1080\/10655140290010097"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000,3,9]]},"references-count":0,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2002,1]]}},"alternative-id":["10.1080\/10655140290010097"],"URL":"https:\/\/doi.org\/10.1080\/10655140290010097","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[2000,3,9]]},"assertion":[{"value":"2000-01-13","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2000-03-09","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}