{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T03:40:01Z","timestamp":1723088401848},"reference-count":0,"publisher":"Wiley","issue":"4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/501100001868","name":"National Science Council","doi-asserted-by":"publisher","award":["NSC 88-2219-E-110-001","80-2215-E-110-014"],"award-info":[{"award-number":["NSC 88-2219-E-110-001","80-2215-E-110-014"]}],"id":[{"id":"10.13039\/501100001868","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2002,1]]},"abstract":"<jats:p>The inner product of two vectors might be one of the most frequently used mathematical operations in digital computation. The design style of inner product processor will become a critical issue of performance. So does its basic building block, i.e. 3\u20102 compressor. In this work, improved designs of 3\u20102 C<jats:sup>2<\/jats:sup>PL\u2010based compressors are presented which can be used to build a fast inner product processor. The features of our compressors include a short delay minimized by HSPICE optimization, less transistor count, and high fan\u2010out.<\/jats:p>","DOI":"10.1080\/10655140290011195","type":"journal-article","created":{"date-parts":[[2002,8,25]],"date-time":"2002-08-25T09:42:24Z","timestamp":1030268544000},"page":"383-388","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Improved Design of C<sup>2<\/sup>PL 3\u20102 Compressors for Inner Product Processing"],"prefix":"10.1155","volume":"14","author":[{"given":"Chua-Chin","family":"Wang","sequence":"first","affiliation":[]},{"given":"Po-Ming","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Chenn-Jung","family":"Huang","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2001,3,16]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2002\/413706.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1080\/10655140290011195","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T02:31:04Z","timestamp":1723084264000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1080\/10655140290011195"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001,3,16]]},"references-count":0,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2002,1]]}},"alternative-id":["10.1080\/10655140290011195"],"URL":"https:\/\/doi.org\/10.1080\/10655140290011195","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[2001,3,16]]},"assertion":[{"value":"1999-05-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2001-03-16","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}