{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,29]],"date-time":"2025-04-29T23:10:02Z","timestamp":1745968202797,"version":"3.40.4"},"reference-count":15,"publisher":"Tech Science Press","issue":"6","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Intelligent Automation & Soft Computing"],"published-print":{"date-parts":[[2011,1]]},"DOI":"10.1080\/10798587.2011.10643186","type":"journal-article","created":{"date-parts":[[2013,3,2]],"date-time":"2013-03-02T08:00:39Z","timestamp":1362211239000},"page":"771-780","source":"Crossref","is-referenced-by-count":0,"title":["Oware: Operand width Aware Redundant Execution for Whole-Processor Error Detection*"],"prefix":"10.32604","volume":"17","author":[{"given":"Yu","family":"Hu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chen","family":"Zhongliang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaowei","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"17807","reference":[{"key":"CIT0001","doi-asserted-by":"crossref","unstructured":"A. Shye, T. Moseley, V. J. Reddi, J. Blomstedt and D. A. Connors, \u201cUsing Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance,\u201dProceedings of DSN, pp. 297\u2013306, 2007.","DOI":"10.1109\/DSN.2007.98"},{"key":"CIT0002","doi-asserted-by":"crossref","unstructured":"S.K. Reinhardt and S.S. Mukherjee, \u201cTransient Fault Detection via Simultaneous Multithreading,\u201dProceedings of ISCA, pp. 25\u201336, 2000.","DOI":"10.1145\/342001.339652"},{"key":"CIT0003","doi-asserted-by":"crossref","unstructured":"S. S. Mukherjee, M. Kontz, and S. K. Reinhardt, \u201cDetailed Design and Evaluation of Redundant Multithreading Alternatives,\u201dProceedings of ISCA, pp. 99\u2013110, May 2002.","DOI":"10.1145\/545214.545227"},{"key":"CIT0005","doi-asserted-by":"crossref","unstructured":"D. M. Tullsen, S. J. Eggers, and H. M. Levy, \u201cSimultaneous Multithreading. Maximizing On-Chip Parallelism,\u201dProceedings of ISCA, pp. 392\u2013403, 1995.","DOI":"10.1145\/225830.224449"},{"key":"CIT0006","unstructured":"T.M. Austin, \u201cDIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design,\u201dProceedings of Micro, pp. 196\u2013207, 1999."},{"key":"CIT0007","doi-asserted-by":"crossref","unstructured":"J.C. Smolens, J. Kim, J.C. Hoe, and B. Falsafi, \u201cEfficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures,\u201dProceedings of Micro, pp. 257\u2013268, 2004.","DOI":"10.1109\/MICRO.2004.19"},{"key":"CIT0008","doi-asserted-by":"crossref","unstructured":"A. Parashar, S. Gurumurihi, and A. Sivasubramaniam, \u201cA Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy,\u201dProceedings of ISCA, pp. 376\u2013386, 2004.","DOI":"10.1145\/1028176.1006732"},{"key":"CIT0009","unstructured":"S. Kumar and A. Aggarwal, \u201cReducing Resource Redundancy for Concurrent Error Detection Techniques in High Performance Microprocessors,\u201dProceedings of HPCA, pp. 212\u2013221, 2006."},{"key":"CIT0011","doi-asserted-by":"crossref","unstructured":"G.A. Reis, J. Chang, N. Vachharajani, R. Rangan, and D.I. August, \u201cSWIFT: Software Implemented Fault Tolerance,\u201dProceedings of CGO, pp. 243\u2013254, 2005.","DOI":"10.1109\/CGO.2005.34"},{"key":"CIT0012","doi-asserted-by":"crossref","unstructured":"G.A. Reis, J. Chang, N. Vachharajani, R. Rangan, D.I. August, and S.S. Mukherjee, \u201cDesign and Evaluation of Hybrid Fault-Detection Systems,\u201dProceedings of ISCA, pp. 148\u2013159, 2005.","DOI":"10.1145\/1080695.1069983"},{"key":"CIT0013","unstructured":"J. Hu, S. Wang, and S. G. Ziavras, \u201cIn-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability,\u201dProceedings of DSN, pp. 281\u2013290, 2006."},{"key":"CIT0015","doi-asserted-by":"crossref","unstructured":"D. Brooks and M. Martonosi, \u201cDynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance\u201d,Proceedings of HPCA, pp. 13\u201322, 1999.","DOI":"10.1109\/HPCA.1999.744314"},{"key":"CIT0016","doi-asserted-by":"crossref","unstructured":"O. Ergin, D. Balkan, K. Ghose, and D. Ponomarev, \u201cRegister Packing Exploiting Narrow-Width Operands for Reducing Register File Pressure,\u201dProceedings of Micro, pp. 304\u2013315, 2004.","DOI":"10.1109\/MICRO.2004.29"},{"key":"CIT0017","doi-asserted-by":"crossref","unstructured":"D. Burger and T.M. Austin, \u201cThe SimpleScalar Tool Set: Version 2.0,\u201d Technical Report, Univ. of Wisconsin-Madison, Madison, Wisconsin, 1997.","DOI":"10.1145\/268806.268810"},{"key":"CIT0018","doi-asserted-by":"crossref","unstructured":"T. Sherwood, E. Perelman, G. Hamerly, and B. Calder, \u201cAutomatically Characterizing Large Scale Program Behavior,\u201dProceedings of ASPLOS, pp. 45\u201357, 2002.","DOI":"10.1145\/605432.605403"}],"container-title":["Intelligent Automation & Soft Computing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/autosoftjournal.net\/viewPaper.php?paper=10643186","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,29]],"date-time":"2025-04-29T22:50:22Z","timestamp":1745967022000},"score":1,"resource":{"primary":{"URL":"http:\/\/autosoftjournal.net\/paperShow.php?paper=10643186"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,1]]},"references-count":15,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2011,1]]}},"alternative-id":["10.1080\/10798587.2011.10643186"],"URL":"https:\/\/doi.org\/10.1080\/10798587.2011.10643186","relation":{},"ISSN":["1079-8587","2326-005X"],"issn-type":[{"type":"print","value":"1079-8587"},{"type":"electronic","value":"2326-005X"}],"subject":[],"published":{"date-parts":[[2011,1]]}}}