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Comput. Eng."],"published-print":{"date-parts":[[2024,9,1]]},"abstract":"<jats:title>Abstract<\/jats:title>\n               <jats:p>Crossbar arrays of memristors are promising to accelerate the deep learning algorithm as a non-von-Neumann architecture, where the computation happens at the location of the memory. The computations are parallelly conducted employing the basic physical laws. However, current research works mainly focus on the offline training of deep neural networks, i.e. only the information forwarding is accelerated by the crossbar array. Two other essential operations, i.e. error backpropagation and weight update, are mostly simulated and coordinated by a conventional computer in von Neumann architecture, respectively. Several different <jats:italic>in situ<\/jats:italic> learning schemes incorporating error backpropagation and\/or weight updates have been proposed and investigated through neuromorphic simulation. Nevertheless, they met the issues of non-ideal synaptic behaviors of the memristors and the complexities of the neural circuits surrounding crossbar arrays. Here we review the difficulties and approaches in implementing the error backpropagation and weight update operations for online training or in-memory learning that are adapted to noisy and non-ideal memristors. We hope this work will be beneficial for the development of open neuromorphic simulation tools for learning-in-memory systems, and eventually for the hardware implementation of such as system.<\/jats:p>","DOI":"10.1088\/2634-4386\/ad6732","type":"journal-article","created":{"date-parts":[[2024,7,24]],"date-time":"2024-07-24T23:07:11Z","timestamp":1721862431000},"page":"032002","update-policy":"https:\/\/doi.org\/10.1088\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Difficulties and approaches in enabling learning-in-memory using crossbar arrays of memristors"],"prefix":"10.1088","volume":"4","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7206-8659","authenticated-orcid":true,"given":"Wei","family":"Wang","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9820-0016","authenticated-orcid":true,"given":"Yang","family":"Li","sequence":"additional","affiliation":[]},{"given":"Ming","family":"Wang","sequence":"additional","affiliation":[]}],"member":"266","published-online":{"date-parts":[[2024,8,1]]},"reference":[{"key":"ncead6732bib1","doi-asserted-by":"publisher","first-page":"929","DOI":"10.1109\/IJCNN.2016.7727298","article-title":"Resistive memory device requirements for a neural algorithm accelerator","volume":"vol 2016","author":"Agarwal","year":"2016"},{"key":"ncead6732bib2","doi-asserted-by":"publisher","first-page":"2408","DOI":"10.1109\/TNNLS.2014.2383395","article-title":"Memristor-based multilayer neural networks with online gradient descent training","volume":"26","author":"Soudry","year":"2015","journal-title":"IEEE Trans. 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