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Eng."],"published-print":{"date-parts":[[2025,6,1]]},"abstract":"<jats:title>Abstract<\/jats:title>\n               <jats:p>The conventional computing platforms based on von-Neumann architecture are highly space- and energy-intensive while handling the emerging applications such as AI, ML, and big data. To overcome the von Neumann bottleneck, compact and light-weight logic-in-memory (LiM) implementations of Boolean logic gates based on emerging non-volatile memory (e-NVM) such as RRAMs, PCM, STT-MRAMs, etc were proposed recently. However, these e-NVMs not only exhibit significant temporal and spatial variability, but their large-scale integration with CMOS process is also a technological challenge. To overcome these issues with the emerging non-volatile memories, ferroelectric FETs based on CMOS-compatible doped hafnium oxide with the capability of large-scale CMOS integration in the advanced logic nodes were proposed. Considering the high scalability and CMOS-compatibility of the FeFETs, in this work, for the first time, we propose a LiM implementation utilizing a single ferroelectric fully-depleted-silicon-on-insulator (Fe-FDSOI) FET exploiting the unique drain erase phenomenon. In our proposed LiM implementation, inputs are applied at the gate and drain terminals using a novel input-to-voltage mapping scheme, and output is obtained as the current flowing through the Fe-FDSOI FET. We utilize an experimentally calibrated compact model of the ferroelectric capacitor connected to the baseline industry standard BSIM-IMG compact model for the FDSOI transistor for proof of concept demonstration. We also perform a comprehensive analysis of the performance metrics of the proposed LiM implementation. Our results indicate that we can realize at least 10 Boolean logic gates with high energy and area-efficiency utilizing the proposed scheme.<\/jats:p>","DOI":"10.1088\/2634-4386\/adce28","type":"journal-article","created":{"date-parts":[[2025,4,17]],"date-time":"2025-04-17T22:50:41Z","timestamp":1744930241000},"page":"024007","update-policy":"https:\/\/doi.org\/10.1088\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Exploiting drain-erase scheme in ferroelectric FETs for logic-in-memory"],"prefix":"10.1088","volume":"5","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1715-8301","authenticated-orcid":true,"given":"Musaib","family":"Rafiq","sequence":"first","affiliation":[]},{"given":"Yogesh Singh","family":"Chauhan","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9992-3240","authenticated-orcid":true,"given":"Shubham","family":"Sahay","sequence":"additional","affiliation":[]}],"member":"266","published-online":{"date-parts":[[2025,5,6]]},"reference":[{"key":"nceadce28bib1","doi-asserted-by":"publisher","first-page":"65","DOI":"10.1089\/omi.2017.0194","article-title":"Birth of industry 5.0: making sense of big data with artificial intelligence, \u2018the internet of things\u2019 and next-generation technology policy","volume":"22","author":"\u00d6zdemir","year":"2018","journal-title":"OMICS: J. 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