{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,6]],"date-time":"2026-04-06T01:50:30Z","timestamp":1775440230408,"version":"3.50.1"},"publisher-location":"Providence, Rhode Island","reference-count":0,"publisher":"American Mathematical Society","isbn-type":[{"value":"9780821865941","type":"print"},{"value":"9780821870747","type":"print"},{"value":"9781470439613","type":"print"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1991,6,6]]},"DOI":"10.1090\/dimacs\/003\/30","type":"book-chapter","created":{"date-parts":[[2017,4,26]],"date-time":"2017-04-26T22:31:20Z","timestamp":1493245880000},"page":"493-504","source":"Crossref","is-referenced-by-count":0,"title":["A data path verifier for register transfer level using temporal logic language Tokio"],"prefix":"10.1090","author":[{"given":"H.","family":"Nakamura","sequence":"first","affiliation":[]},{"given":"Y.","family":"Kukimoto","sequence":"additional","affiliation":[]},{"given":"M.","family":"Fujita","sequence":"additional","affiliation":[]},{"given":"H.","family":"Tanaka","sequence":"additional","affiliation":[]}],"member":"14","container-title":["DIMACS Series in Discrete Mathematics and Theoretical Computer Science","Computer-Aided Verification \u201990"],"original-title":[],"language":"en","deposited":{"date-parts":[[2026,4,6]],"date-time":"2026-04-06T00:54:47Z","timestamp":1775436887000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.ams.org\/dimacs\/003"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1991,6,6]]},"ISBN":["9780821865941","9780821870747","9781470439613"],"references-count":0,"URL":"https:\/\/doi.org\/10.1090\/dimacs\/003\/30","relation":{},"ISSN":["1052-1798","2472-4793"],"issn-type":[{"value":"1052-1798","type":"print"},{"value":"2472-4793","type":"electronic"}],"subject":[],"published":{"date-parts":[[1991,6,6]]}}}