{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,30]],"date-time":"2022-03-30T15:48:12Z","timestamp":1648655292362},"reference-count":12,"publisher":"Oxford University Press (OUP)","issue":"6","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2005,11,1]]},"DOI":"10.1093\/comjnl\/bxh104","type":"journal-article","created":{"date-parts":[[2005,5,14]],"date-time":"2005-05-14T00:13:45Z","timestamp":1116029625000},"page":"667-676","source":"Crossref","is-referenced-by-count":1,"title":["Probabilistic Estimation for Routing Space"],"prefix":"10.1093","volume":"48","author":[{"given":"Fei","family":"He","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ming","family":"Gu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaoyu","family":"Song","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhiwei","family":"Tang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guowu","family":"Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lerong","family":"Cheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"286","published-online":{"date-parts":[[2005,5,13]]},"reference":[{"key":"key\n\t\t\t\t20171011172531_B1","doi-asserted-by":"crossref","unstructured":"Sutherland, N. and Oesticher, N. (1973) How big should a printed circuit board be? IEEE Trans. Comput., C-22, 537\u2013741.","DOI":"10.1109\/T-C.1973.223759"},{"key":"key\n\t\t\t\t20171011172531_B2","doi-asserted-by":"crossref","unstructured":"Gamal, A. (1981) Two-dimensional stochastic model for interconnections in master slice integrated circuits. IEEE Trans. Circuits Syst., CAS I-28 (2), 127\u2013138.","DOI":"10.1109\/TCS.1981.1084958"},{"key":"key\n\t\t\t\t20171011172531_B3","doi-asserted-by":"crossref","unstructured":"Gamal, A. and Syed, Z. (1981) A stochastic model for interconnections in custom integrated circuits. IEEE Trans. Circuits Syst., CAS I-28, 888\u2013894.","DOI":"10.1109\/TCS.1981.1085064"},{"key":"key\n\t\t\t\t20171011172531_B4","doi-asserted-by":"crossref","unstructured":"Kurdahi, F. and Parker, A. (1986) Techniques for area estimation of VLSI layouts. IEEE Trans. Comput. Aid. D., 8(1), 81.","DOI":"10.1109\/43.21821"},{"key":"key\n\t\t\t\t20171011172531_B5","unstructured":"Heller, W., Mikhail, W. and Donath, W. (1980) Prediction of wiring space requirements of LSI. J. Des. Autom. Fault, 2 (2), 117\u2013144."},{"key":"key\n\t\t\t\t20171011172531_B6","doi-asserted-by":"crossref","unstructured":"Song, X., Tang, Q., Zhou, D. and Wang, Y. (2000) Wire space estimation and routability analysis. IEEE Trans. Comput. Aid. D., 19(5), 624\u2013628.","DOI":"10.1109\/43.845089"},{"key":"key\n\t\t\t\t20171011172531_B7","doi-asserted-by":"crossref","unstructured":"Cho, J. (2000) Wiring space and length estimation in two-dimensional arrays. IEEE Trans. Comput. Aid. D., 19(5), 612\u2013615.","DOI":"10.1109\/43.845086"},{"key":"key\n\t\t\t\t20171011172531_B8","doi-asserted-by":"crossref","unstructured":"Lou, J., Thakur, S., Krishnamoorthy, S. and Sheng, H. (2002) Estimating routing congestion using probabilistic analysis. IEEE Trans. Comput. Aid. D., 21(1), 32\u201341.","DOI":"10.1109\/43.974135"},{"key":"key\n\t\t\t\t20171011172531_B9","unstructured":"Cheng, L., Song, X., Yang, G. and Tang, Z. (2004) A fast congestion estimator for routing with bounded detours. In Proc. ASP-DAC 2004, Yokohama, Japan, January 27\u201330, pp. 666\u2013670. IEEE, USA."},{"key":"key\n\t\t\t\t20171011172531_B10","unstructured":"Cheng, L., Hung, W., Yang, G. and Song, X. (2004) Congestion Estimation for 3D Routing. In Proc. ISVLSI 2004, Lafayette, LA, February 19\u201320, pp. 239\u2013240. IEEE Computer Society, USA."},{"key":"key\n\t\t\t\t20171011172531_B11","doi-asserted-by":"crossref","unstructured":"Burstein, M. and Pelavin, R. (1983) Hierarchical wire routing. IEEE Trans. Comput. Aid. D., 2(4), 223\u2013234.","DOI":"10.1109\/TCAD.1983.1270040"},{"key":"key\n\t\t\t\t20171011172531_B12","unstructured":"UCLA, http:\/\/www.ece.ucsb.edu\/~kastner\/labyrinth\/."}],"container-title":["The Computer Journal"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/academic.oup.com\/comjnl\/article-pdf\/48\/6\/667\/1025624\/bxh104.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,4,7]],"date-time":"2020-04-07T09:51:49Z","timestamp":1586253109000},"score":1,"resource":{"primary":{"URL":"http:\/\/academic.oup.com\/comjnl\/article\/48\/6\/667\/358262\/Probabilistic-Estimation-for-Routing-Space"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,5,13]]},"references-count":12,"journal-issue":{"issue":"6","published-online":{"date-parts":[[2005,5,13]]},"published-print":{"date-parts":[[2005,11,1]]}},"URL":"https:\/\/doi.org\/10.1093\/comjnl\/bxh104","relation":{},"ISSN":["1460-2067","0010-4620"],"issn-type":[{"value":"1460-2067","type":"electronic"},{"value":"0010-4620","type":"print"}],"subject":[],"published-other":{"date-parts":[[2005,11]]},"published":{"date-parts":[[2005,5,13]]}}}