{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T13:00:06Z","timestamp":1740142806183,"version":"3.37.3"},"reference-count":23,"publisher":"Oxford University Press (OUP)","issue":"6","license":[{"start":{"date-parts":[[2017,10,27]],"date-time":"2017-10-27T00:00:00Z","timestamp":1509062400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/academic.oup.com\/journals\/pages\/about_us\/legal\/notices"}],"funder":[{"name":"Spanish government","award":["TIN2012-32180","TIN2015-65277-R","TIN2015-65316-P"],"award-info":[{"award-number":["TIN2012-32180","TIN2015-65277-R","TIN2015-65316-P"]}]},{"name":"HIPEAC-4 European Network of Excellence"},{"DOI":"10.13039\/501100005298","name":"University of Costa Rica","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100005298","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100007225","name":"Costa Rican Ministry of Science and Technology MICIT and CONICIT","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100007225","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100005993","name":"National Council for Scientific Research","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100005993","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,6,1]]},"DOI":"10.1093\/comjnl\/bxx099","type":"journal-article","created":{"date-parts":[[2017,9,29]],"date-time":"2017-09-29T07:08:27Z","timestamp":1506668907000},"page":"856-880","source":"Crossref","is-referenced-by-count":3,"title":["Reuse Detector: Improving the Management of STT-RAM SLLCs"],"prefix":"10.1093","volume":"61","author":[{"given":"R","family":"Rodr\u00edguez-Rodr\u00edguez","sequence":"first","affiliation":[{"name":"ArTeCS Group, Facultad de Informatica, University Complutense of Madrid, Madrid, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J","family":"D\u00edaz","sequence":"additional","affiliation":[{"name":"Computer Architecture Group, University of Zaragoza, Zaragoza, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2773-3023","authenticated-orcid":false,"given":"F","family":"Castro","sequence":"additional","affiliation":[{"name":"ArTeCS Group, Facultad de Informatica, University Complutense of Madrid, Madrid, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P","family":"Ib\u00e1\u00f1ez","sequence":"additional","affiliation":[{"name":"Computer Architecture Group, University of Zaragoza, Zaragoza, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D","family":"Chaver","sequence":"additional","affiliation":[{"name":"ArTeCS Group, Facultad de Informatica, University Complutense of Madrid, Madrid, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V","family":"Vi\u00f1als","sequence":"additional","affiliation":[{"name":"Computer Architecture Group, University of Zaragoza, Zaragoza, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1343-7108","authenticated-orcid":false,"given":"J C","family":"Saez","sequence":"additional","affiliation":[{"name":"ArTeCS Group, Facultad de Informatica, University Complutense of Madrid, Madrid, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0687-3737","authenticated-orcid":false,"given":"M","family":"Prieto-Matias","sequence":"additional","affiliation":[{"name":"ArTeCS Group, Facultad de Informatica, University Complutense of Madrid, Madrid, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L","family":"Pi\u00f1uel","sequence":"additional","affiliation":[{"name":"ArTeCS Group, Facultad de Informatica, University Complutense of Madrid, Madrid, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T","family":"Monreal","sequence":"additional","affiliation":[{"name":"Department of Computer Architecture, Technical University of Catalonia, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J M","family":"Llaber\u00eda","sequence":"additional","affiliation":[{"name":"Department of Computer Architecture, Technical University of Catalonia, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"286","published-online":{"date-parts":[[2017,10,27]]},"reference":[{"year":"2014","author":"Ahn","key":"key\n\t\t\t\t20180601110859_bxx099C1"},{"year":"2010","author":"Khan","key":"key\n\t\t\t\t20180601110859_bxx099C2"},{"key":"key\n\t\t\t\t20180601110859_bxx099C3","first-page":"38:1","article-title":"Exploiting reuse locality on inclusive shared last-level caches","volume":"9","author":"Albericio","year":"2013","journal-title":"ACM Trans. Archit. Code Optim."},{"year":"2013","author":"Albericio","key":"key\n\t\t\t\t20180601110859_bxx099C4"},{"year":"2013","key":"key\n\t\t\t\t20180601110859_bxx099C5"},{"key":"key\n\t\t\t\t20180601110859_bxx099C6","first-page":"994","article-title":"NVSim: a circuit-level performance, energy, and area model for emerging nonvolatile memory","volume":"31","author":"Dong","year":"2012","journal-title":"IEEE Trans. Compt.-Aided Design Integr. Circuits Syst."},{"year":"2015","author":"D\u00edaz","key":"key\n\t\t\t\t20180601110859_bxx099C7"},{"key":"key\n\t\t\t\t20180601110859_bxx099C8","first-page":"1","article-title":"The gem5 simulator","volume":"39","author":"Binkert","year":"2011","journal-title":"ACM SIGARCH Comput. Architecture News"},{"year":"2014","author":"Chang","key":"key\n\t\t\t\t20180601110859_bxx099C9"},{"year":"2009","author":"Agarwal","key":"key\n\t\t\t\t20180601110859_bxx099C10"},{"key":"key\n\t\t\t\t20180601110859_bxx099C11","first-page":"16","article-title":"Dramsim2: A cycle accurate memory system simulator","volume":"10","author":"Rosenfeld","year":"2011","journal-title":"Comput. Architecture Lett."},{"year":"2013","key":"key\n\t\t\t\t20180601110859_bxx099C12"},{"year":"2004","author":"Patil","key":"key\n\t\t\t\t20180601110859_bxx099C13"},{"year":"2013","author":"Wang","key":"key\n\t\t\t\t20180601110859_bxx099C14"},{"year":"2011","author":"Rasquinha","key":"key\n\t\t\t\t20180601110859_bxx099C15"},{"key":"key\n\t\t\t\t20180601110859_bxx099C16","first-page":"73","article-title":"Coding last level stt-ram cache for high endurance and low power","volume":"13","author":"Yazdanshenas","year":"2014","journal-title":"IEEE Comput. Architecture Lett."},{"year":"2013","author":"Jung","key":"key\n\t\t\t\t20180601110859_bxx099C17"},{"year":"2012","author":"Park","key":"key\n\t\t\t\t20180601110859_bxx099C18"},{"year":"2013","author":"Mao","key":"key\n\t\t\t\t20180601110859_bxx099C19"},{"year":"2012","author":"Jog","key":"key\n\t\t\t\t20180601110859_bxx099C20"},{"year":"2010","author":"Guo","key":"key\n\t\t\t\t20180601110859_bxx099C21"},{"year":"2011","author":"Sun","key":"key\n\t\t\t\t20180601110859_bxx099C22"},{"year":"2009","author":"Sun","key":"key\n\t\t\t\t20180601110859_bxx099C23"}],"container-title":["The Computer Journal"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/academic.oup.com\/comjnl\/article-pdf\/61\/6\/856\/24979116\/bxx099.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,6,1]],"date-time":"2018-06-01T11:11:36Z","timestamp":1527851496000},"score":1,"resource":{"primary":{"URL":"https:\/\/academic.oup.com\/comjnl\/article\/61\/6\/856\/4568418"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10,27]]},"references-count":23,"journal-issue":{"issue":"6","published-online":{"date-parts":[[2017,10,27]]},"published-print":{"date-parts":[[2018,6,1]]}},"URL":"https:\/\/doi.org\/10.1093\/comjnl\/bxx099","relation":{},"ISSN":["0010-4620","1460-2067"],"issn-type":[{"type":"print","value":"0010-4620"},{"type":"electronic","value":"1460-2067"}],"subject":[],"published-other":{"date-parts":[[2018,6]]},"published":{"date-parts":[[2017,10,27]]}}}