{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:16:10Z","timestamp":1763468170038,"version":"3.28.0"},"reference-count":25,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/3dic.2013.6702342","type":"proceedings-article","created":{"date-parts":[[2014,1,10]],"date-time":"2014-01-10T15:09:52Z","timestamp":1389366592000},"page":"1-8","source":"Crossref","is-referenced-by-count":3,"title":["Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology"],"prefix":"10.1109","author":[{"given":"Vinod","family":"Pangracious","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Habib","family":"Mehrez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zied","family":"Marakchi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDERC.2012.6343325"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2007.373897"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2012.6330588"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.78"},{"key":"16","first-page":"90","article-title":"Through Silicon Via-Based Grid for Thermal Control in 3D Chips","author":"ayala","year":"2009","journal-title":"Nanonets"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/2483028.2483130"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAPT.2002.808011"},{"key":"11","article-title":"Architecture Level Exploration of Alternative schmes Targeting 3D FPGAs: A Software Supported Methodology","volume":"2008","author":"siozios","year":"0","journal-title":"International Journal of Reconfigurable Computing"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.150"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117219"},{"key":"20","first-page":"279","article-title":"Assembly and Reliability Challenges in 3D Integration of 28nm FPGA Die on a Large High Density 65nm Passive Interposer","author":"chaware","year":"2012","journal-title":"ECTC"},{"journal-title":"\"International Technology Roadmap for Semiconductors \" [Online]","first-page":"17","year":"2012","key":"22"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.2007473"},{"key":"24","doi-asserted-by":"crossref","first-page":"206","DOI":"10.1145\/341800.341824","article-title":"Compact, Multilayer Layout for Butterfly Fat-Tree","author":"dehon","year":"2000","journal-title":"SPAA '00"},{"key":"25","article-title":"Architectural Exploration of 3D FPGAs Towards A Better Balance Between Area and Delay","author":"chen","year":"2011","journal-title":"DATE11"},{"journal-title":"Reconfigurable Architectures for General-Purpose Computing","year":"1996","author":"dehon","key":"3"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117205"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1155\/2009\/259837"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-2742-8"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/1572471.1572486"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/92.902261"},{"key":"5","first-page":"100","article-title":"The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density","author":"ahmed","year":"2003","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/503048.503072"},{"journal-title":"Techniques for producing 3D ICs with high-density interconnect","year":"2005","author":"gupta","key":"9"},{"key":"8","first-page":"197","author":"pangracious","year":"2013","journal-title":"Performance Analysis and Optimization of High Density Tree-based 3D Multilevel FPGA"}],"event":{"name":"2013 IEEE International 3D Systems Integration Conference (3DIC)","start":{"date-parts":[[2013,10,2]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2013,10,4]]}},"container-title":["2013 IEEE International 3D Systems Integration Conference (3DIC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6690582\/6702313\/06702342.pdf?arnumber=6702342","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T01:51:16Z","timestamp":1498096276000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6702342\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/3dic.2013.6702342","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}