{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T20:42:17Z","timestamp":1729629737188,"version":"3.28.0"},"reference-count":40,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/3dic.2013.6702347","type":"proceedings-article","created":{"date-parts":[[2014,1,10]],"date-time":"2014-01-10T20:09:52Z","timestamp":1389384592000},"page":"1-8","source":"Crossref","is-referenced-by-count":1,"title":["A high-performance multiported L2 memory IP for scalable three-dimensional integration"],"prefix":"10.1109","author":[{"given":"Erfan","family":"Azarkhish","sequence":"first","affiliation":[]},{"given":"Igor","family":"Loi","sequence":"additional","affiliation":[]},{"given":"Luca","family":"Benini","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","article-title":"Techniques for producing 3-d ics with high-density interconnect","author":"gupta","year":"0","journal-title":"Int VLSI Multi-Level Interconnect Conf Waikoloa Beach HI USA 2004"},{"key":"35","article-title":"Parsec 2.0: A new benchmark suite for chip-multiprocessors","author":"bienia","year":"0","journal-title":"Proceedings of the 5th Annual Workshop on Modeling Benchmarking and Simulation June 2009"},{"journal-title":"Novathor Platform [Online]","year":"2012","key":"17"},{"key":"36","first-page":"63","article-title":"A 4.6tbits\/s 3.6ghz single-cycle noc router with a novel switch allocator in 65nm cmos","author":"kumar","year":"2007","journal-title":"ICCD"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"key":"33","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176969"},{"journal-title":"Snapdragon S4 Processors [Online]","year":"2012","key":"15"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"journal-title":"Omap 5 Platform [Online]","year":"2011","key":"16"},{"key":"39","doi-asserted-by":"crossref","first-page":"1414","DOI":"10.1109\/DATE.2008.4484872","article-title":"Developing mesochronous synchronizers to enable 3d nocs","author":"loi","year":"2008","journal-title":"Design Automation and Test in Europe 2008 DATE '08"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457194"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2012.6379047"},{"key":"37","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672170"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/NoCS.2013.6558394"},{"key":"38","doi-asserted-by":"publisher","DOI":"10.1145\/2287696.2287703"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977307"},{"journal-title":"Roadmap for Design and Eda Infrastructure for 3d Products [Online]","year":"2012","author":"radojcic","key":"21"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5434016"},{"key":"40","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2013.4"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISoC.2011.6081643"},{"key":"23","first-page":"130","article-title":"Design and management of 3d chip multiprocessors using network-in-memory","author":"li","year":"2006","journal-title":"Computer Architecture 2006 ISCA '06 33rd International Symposium on"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.13"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.893649"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.142"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2012.2193936"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2010.5751440"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416628"},{"key":"3","doi-asserted-by":"crossref","first-page":"453","DOI":"10.1109\/ISCA.2008.15","article-title":"3d-stacked memory architectures for multi-core processors","author":"loh","year":"2008","journal-title":"Computer Architecture 2008 ISCA '08 35th International Symposium On"},{"key":"2","doi-asserted-by":"crossref","first-page":"140","DOI":"10.1145\/1555815.1555774","article-title":"Rigel: An architecture and scalable programming interface for a 1000-core accelerator","volume":"37","author":"kelm","year":"2009","journal-title":"SIGARCH Comput Archit News"},{"key":"10","doi-asserted-by":"crossref","first-page":"587","DOI":"10.1145\/1629911.1630062","article-title":"no cache-coherence: a single-cycle ring interconnection for multi-core l1-nuca sharing on 3d chips","author":"shu-hsuan chou","year":"2009","journal-title":"2009 46th ACM\/IEEE Design Automation Conference dac"},{"key":"1","doi-asserted-by":"crossref","first-page":"746","DOI":"10.1145\/1278480.1278667","article-title":"Thousand core chips: A technology perspective","author":"borkar","year":"2007","journal-title":"DAC '07"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746413"},{"key":"7","article-title":"Dram scaling & bandwidth challenges","author":"sandhu","year":"0","journal-title":"NSF Workshop on Emerging Tech for Interconnects (WETI) Feb 2012"},{"key":"6","doi-asserted-by":"crossref","first-page":"991","DOI":"10.1145\/1146909.1147160","article-title":"A thermally-aware performance analysis of vertically integrated (3-d) processor-memory hierarchy","author":"loi","year":"2006","journal-title":"Design Automation Conference 2006 43rd ACM\/IEEE"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228477"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.134"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2017750"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.2001.954688"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798261"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/1973009.1973028"}],"event":{"name":"2013 IEEE International 3D Systems Integration Conference (3DIC)","start":{"date-parts":[[2013,10,2]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2013,10,4]]}},"container-title":["2013 IEEE International 3D Systems Integration Conference (3DIC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6690582\/6702313\/06702347.pdf?arnumber=6702347","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T09:20:48Z","timestamp":1565083248000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6702347\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":40,"URL":"https:\/\/doi.org\/10.1109\/3dic.2013.6702347","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}