{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,6]],"date-time":"2026-01-06T13:19:43Z","timestamp":1767705583818},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,8]]},"DOI":"10.1109\/3dic.2015.7334555","type":"proceedings-article","created":{"date-parts":[[2015,11,23]],"date-time":"2015-11-23T22:46:57Z","timestamp":1448318817000},"page":"TS2.2.1-TS2.2.4","source":"Crossref","is-referenced-by-count":12,"title":["Electrical performance of high bandwidth memory (HBM) interposer channel in terabyte\/s bandwidth graphics module"],"prefix":"10.1109","author":[{"given":"Hyunsuk","family":"Lee","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kyungjun","family":"Cho","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Heegon","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sumin","family":"Choi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jaemin","family":"Lim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joungho","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"1","article-title":"Xilinx stacked silicon interconnect technology delivers breakthrough fpga capacity, bandwidth, and power efficiency","author":"dorsey","year":"2010","journal-title":"Xilinx White Paper Vertex-7 FPGAs"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2012.6248842"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2012.6248844"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"847","DOI":"10.1109\/ECTC.2008.4550075","article-title":"Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring","author":"sunohara","year":"2008","journal-title":"Electronic Components and Technology Conference 2008 ECTC 2008 58th"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2011.5898571"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2012.2204392"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"19","DOI":"10.1145\/1127908.1127915","article-title":"Thermal analysis of a 3D die-stacked high-performance microprocessor","author":"puttaswamy","year":"2006","journal-title":"Proceedings of the 16th ACM Great Lakes symposium on VLSI"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2013.6575675"},{"year":"0","key":"ref1"}],"event":{"name":"2015 International 3D Systems Integration Conference (3DIC)","start":{"date-parts":[[2015,8,31]]},"location":"Sendai, Japan","end":{"date-parts":[[2015,9,2]]}},"container-title":["2015 International 3D Systems Integration Conference (3DIC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7328029\/7334459\/07334555.pdf?arnumber=7334555","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,24]],"date-time":"2017-06-24T00:14:26Z","timestamp":1498263266000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7334555\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,8]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/3dic.2015.7334555","relation":{},"subject":[],"published":{"date-parts":[[2015,8]]}}}