{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T09:34:56Z","timestamp":1725615296933},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,11]]},"DOI":"10.1109\/3dic.2016.7970036","type":"proceedings-article","created":{"date-parts":[[2017,7,10]],"date-time":"2017-07-10T21:54:38Z","timestamp":1499723678000},"page":"1-5","source":"Crossref","is-referenced-by-count":2,"title":["Physical design of a 3D-stacked heterogeneous multi-core processor"],"prefix":"10.1109","author":[{"given":"Randy","family":"Widialaksono","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rangeen","family":"Basu Roy Chowdhury","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhenqian","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joshua","family":"Schabel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steve","family":"Lipa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eric","family":"Rotenberg","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"W.","family":"Rhett Davis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paul","family":"Franzon","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2012.6263013"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000067"},{"journal-title":"Design of On-chip Bus of Heterogeneous 3DIC Microprocessors","year":"2016","author":"zhang","key":"ref10"},{"journal-title":"Phase ii implementation and verification of the h3 processor","year":"2015","author":"srinivasan","key":"ref6"},{"key":"ref5","article-title":"Diram architecture overview","author":"chapman","year":"2014","journal-title":"Tezzaron Semiconductor"},{"journal-title":"Three-Dimensional Integration of Heterogeneous Multi-Core Processors","year":"2016","author":"widialaksono","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2014.7152172"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2015.7477478"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2013.6702399"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657038"}],"event":{"name":"2016 IEEE International 3D Systems Integration Conference (3DIC)","start":{"date-parts":[[2016,11,8]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2016,11,11]]}},"container-title":["2016 IEEE International 3D Systems Integration Conference (3DIC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7959775\/7969992\/07970036.pdf?arnumber=7970036","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,8,16]],"date-time":"2017-08-16T15:38:40Z","timestamp":1502897920000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7970036\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,11]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/3dic.2016.7970036","relation":{},"subject":[],"published":{"date-parts":[[2016,11]]}}}