{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,10,27]],"date-time":"2023-10-27T14:48:50Z","timestamp":1698418130998},"reference-count":9,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[1992,4,1]],"date-time":"1992-04-01T00:00:00Z","timestamp":702086400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[1992,4]]},"DOI":"10.1109\/4.126557","type":"journal-article","created":{"date-parts":[[2002,8,24]],"date-time":"2002-08-24T20:00:39Z","timestamp":1030219239000},"page":"657-659","source":"Crossref","is-referenced-by-count":17,"title":["An 8.5-ns 112-b transmission gate adder with a conflict-free bypass circuit"],"prefix":"10.1109","volume":"27","author":[{"given":"T.","family":"Sato","sequence":"first","affiliation":[]},{"given":"M.","family":"Sakate","sequence":"additional","affiliation":[]},{"given":"H.","family":"Okada","sequence":"additional","affiliation":[]},{"given":"T.","family":"Sukemura","sequence":"additional","affiliation":[]},{"given":"G.","family":"Goto","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IRETELC.1962.5407919"},{"key":"ref3","first-page":"2","article-title":"Design of a 32bit high-speed adder","volume":"284","author":"kudo","year":"1987","journal-title":"IEICE 70th Anniv Nat Conv Rec"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.1989.72814"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1963.263433"},{"key":"ref8","first-page":"331","author":"weste","year":"1985","journal-title":"Principles of CMOS VLSI Design"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEC.1960.5219821"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/12.57038"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1990.130250"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1987.1676855"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx1\/4\/3538\/00126557.pdf?arnumber=126557","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:06:28Z","timestamp":1638216388000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/126557\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1992,4]]},"references-count":9,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/4.126557","relation":{},"ISSN":["0018-9200"],"issn-type":[{"value":"0018-9200","type":"print"}],"subject":[],"published":{"date-parts":[[1992,4]]}}}