{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,10]],"date-time":"2026-04-10T16:02:54Z","timestamp":1775836974017,"version":"3.50.1"},"reference-count":14,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,11,9]],"date-time":"2020-11-09T00:00:00Z","timestamp":1604880000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,11,9]],"date-time":"2020-11-09T00:00:00Z","timestamp":1604880000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,11,9]],"date-time":"2020-11-09T00:00:00Z","timestamp":1604880000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,11,9]]},"DOI":"10.1109\/a-sscc48613.2020.9336142","type":"proceedings-article","created":{"date-parts":[[2021,2,2]],"date-time":"2021-02-02T22:20:44Z","timestamp":1612304444000},"page":"1-4","source":"Crossref","is-referenced-by-count":16,"title":["0.5V 4.8 pJ\/SOP 0.93\\mu \\mathrm{W}$ Leakage\/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron"],"prefix":"10.1109","author":[{"given":"V. P.","family":"Nambiar","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Pu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Y. K.","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Mani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.","family":"Luo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L.","family":"Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E. K.","family":"Koh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M. M.","family":"Wong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"F.","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"W. L.","family":"Goh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A. T.","family":"Do","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"992","article-title":"A 4096-neuron 1m-synapse 3.8-pj\/sop spiking neural network with on-chip stdp learning and sparse weights in 10-nm finfet cmos","volume":"54","author":"chen","year":"2018","journal-title":"IEEE JSSC"},{"key":"ref11","author":"zhou","year":"2016","journal-title":"DoReFa-Net Training Low Bitwidth Convolutional Neural Networks with Low Bitwidth Gradients"},{"key":"ref12","author":"lecun","year":"1998","journal-title":"The MNIST Database of Handwritten Digits"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2019.8780116"},{"key":"ref14","first-page":"30c","article-title":"A 3.43 tops\/w 48.9 pj\/pixel 50.1 nj\/classification 512 analog neuron sparse coding neural network with on-chip learning and classification in 40nm cmos","author":"buhler","year":"0","journal-title":"IEEE VLSI Symp"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2259038"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702647"},{"key":"ref6","first-page":"145","article-title":"A 0.086-mm2 12.7-pj\/sop 64k-synapse 256-neuron online-learning digital spiking neuromorphic processor in 28-nm cmos","volume":"13","author":"frenkel","year":"2018","journal-title":"IEEE TBioCAS"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.112130359"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3291054"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/j.conb.2004.07.007"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511815706"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"668","DOI":"10.1126\/science.1254642","article-title":"A million spiking-neuron integrated circuit with a scalable communication network and interface","volume":"345","author":"merolla","year":"2014","journal-title":"Science"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2889670"}],"event":{"name":"2020 IEEE Asian Solid-State Circuits Conference (A-SSCC)","location":"Hiroshima, Japan","start":{"date-parts":[[2020,11,9]]},"end":{"date-parts":[[2020,11,11]]}},"container-title":["2020 IEEE Asian Solid-State Circuits Conference (A-SSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9336024\/9336095\/09336142.pdf?arnumber=9336142","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,27]],"date-time":"2022-06-27T15:58:22Z","timestamp":1656345502000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9336142\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,11,9]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/a-sscc48613.2020.9336142","relation":{},"subject":[],"published":{"date-parts":[[2020,11,9]]}}}