{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,14]],"date-time":"2026-04-14T15:47:21Z","timestamp":1776181641834,"version":"3.50.1"},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,11,7]],"date-time":"2021-11-07T00:00:00Z","timestamp":1636243200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,11,7]],"date-time":"2021-11-07T00:00:00Z","timestamp":1636243200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,11,7]],"date-time":"2021-11-07T00:00:00Z","timestamp":1636243200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,11,7]]},"DOI":"10.1109\/a-sscc53895.2021.9634774","type":"proceedings-article","created":{"date-parts":[[2021,12,10]],"date-time":"2021-12-10T20:45:05Z","timestamp":1639169105000},"page":"1-3","source":"Crossref","is-referenced-by-count":1,"title":["Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling"],"prefix":"10.1109","author":[{"given":"Shenggao","family":"Li","sequence":"first","affiliation":[]},{"given":"Chien-Chun","family":"Tsai","sequence":"additional","affiliation":[]},{"given":"Eric","family":"Soenen","sequence":"additional","affiliation":[]},{"given":"Frank J C","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Cheng-Hsiang","family":"Hsieh","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ECOC48923.2020.9333374"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1117\/12.2583395"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2960207"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609253"},{"key":"ref8","year":"0","journal-title":"Specification 2 0"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI51249.2020.00017"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnology18217.2020.9265073"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1117\/12.2584532"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIT.2017.7998183"}],"event":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","location":"Busan, Korea, Republic of","start":{"date-parts":[[2021,11,7]]},"end":{"date-parts":[[2021,11,10]]}},"container-title":["2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9634699\/9634177\/09634774.pdf?arnumber=9634774","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:54:27Z","timestamp":1652201667000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9634774\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,11,7]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/a-sscc53895.2021.9634774","relation":{},"subject":[],"published":{"date-parts":[[2021,11,7]]}}}