{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T10:51:37Z","timestamp":1730199097726,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,11,7]],"date-time":"2021-11-07T00:00:00Z","timestamp":1636243200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,11,7]],"date-time":"2021-11-07T00:00:00Z","timestamp":1636243200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,11,7]],"date-time":"2021-11-07T00:00:00Z","timestamp":1636243200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,11,7]]},"DOI":"10.1109\/a-sscc53895.2021.9634775","type":"proceedings-article","created":{"date-parts":[[2021,12,10]],"date-time":"2021-12-10T20:45:05Z","timestamp":1639169105000},"page":"1-3","source":"Crossref","is-referenced-by-count":4,"title":["A 48 Gb\/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS"],"prefix":"10.1109","author":[{"given":"Kwangho","family":"Lee","sequence":"first","affiliation":[]},{"given":"Woosong","family":"Jung","sequence":"additional","affiliation":[]},{"given":"Haram","family":"Ju","sequence":"additional","affiliation":[]},{"given":"Jinhyung","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Deog-Kyoon","family":"Jeong","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433823"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2018.8502377"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1976.1093326"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2018.8579286"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2744661"},{"key":"ref3","first-page":"871","article-title":"Design Techniques for a 60 Gb\/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology","volume":"51","author":"han","year":"2016","journal-title":"JSSC"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2907804"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2017.8240223"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/A-SSCC53895.2021.9634737"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSICircuits18222.2020.9162791"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2987690"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7062987"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/A-SSCC47793.2019.9056953"}],"event":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","start":{"date-parts":[[2021,11,7]]},"location":"Busan, Korea, Republic of","end":{"date-parts":[[2021,11,10]]}},"container-title":["2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9634699\/9634177\/09634775.pdf?arnumber=9634775","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:54:27Z","timestamp":1652201667000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9634775\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,11,7]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/a-sscc53895.2021.9634775","relation":{},"subject":[],"published":{"date-parts":[[2021,11,7]]}}}