{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,11,19]],"date-time":"2024-11-19T18:30:28Z","timestamp":1732041028318},"reference-count":8,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,11,7]],"date-time":"2021-11-07T00:00:00Z","timestamp":1636243200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,11,7]],"date-time":"2021-11-07T00:00:00Z","timestamp":1636243200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,11,7]],"date-time":"2021-11-07T00:00:00Z","timestamp":1636243200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,11,7]]},"DOI":"10.1109\/a-sscc53895.2021.9634797","type":"proceedings-article","created":{"date-parts":[[2021,12,10]],"date-time":"2021-12-10T20:45:05Z","timestamp":1639169105000},"page":"1-3","source":"Crossref","is-referenced-by-count":8,"title":["A 48 TOPS and 20943 TOPS\/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration"],"prefix":"10.1109","author":[{"given":"Chih-Sheng","family":"Lin","sequence":"first","affiliation":[]},{"given":"Fu-Cheng","family":"Tsai","sequence":"additional","affiliation":[]},{"given":"Jian-Wei","family":"Su","sequence":"additional","affiliation":[]},{"given":"Sih-Han","family":"Li","sequence":"additional","affiliation":[]},{"given":"Tian-Sheuan","family":"Chang","sequence":"additional","affiliation":[]},{"given":"Shyh-Shyuan","family":"Sheu","sequence":"additional","affiliation":[]},{"given":"Wei-Chung","family":"Lo","sequence":"additional","affiliation":[]},{"given":"Shih-Chieh","family":"Chang","sequence":"additional","affiliation":[]},{"given":"Chih-I","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Tuo-Hung","family":"Hou","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2963616"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3066520"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2018.8357071"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3038616"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993565"},{"key":"ref7","first-page":"222","article-title":"An always-on 3.8uJ\/86% CIFAR-10 mixed signal binary CNN processor with all memory on chip in 28nm CMOS","author":"bankman","year":"2018","journal-title":"ISSCC"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2778702"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2899730"}],"event":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","start":{"date-parts":[[2021,11,7]]},"location":"Busan, Korea, Republic of","end":{"date-parts":[[2021,11,10]]}},"container-title":["2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9634699\/9634177\/09634797.pdf?arnumber=9634797","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:54:28Z","timestamp":1652201668000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9634797\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,11,7]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/a-sscc53895.2021.9634797","relation":{},"subject":[],"published":{"date-parts":[[2021,11,7]]}}}