{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,25]],"date-time":"2026-06-25T17:40:17Z","timestamp":1782409217959,"version":"3.54.5"},"reference-count":40,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2016,1,1]],"date-time":"2016-01-01T00:00:00Z","timestamp":1451606400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/OAPA.html"}],"funder":[{"name":"Department of Science and Technology (Science and Engineering Research Board), India"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2016]]},"DOI":"10.1109\/access.2016.2552058","type":"journal-article","created":{"date-parts":[[2016,4,7]],"date-time":"2016-04-07T19:39:50Z","timestamp":1460057990000},"page":"2198-2215","source":"Crossref","is-referenced-by-count":63,"title":["Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis"],"prefix":"10.1109","volume":"4","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8215-7903","authenticated-orcid":false,"given":"Anirban","family":"Sengupta","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Saumya","family":"Bhadauria","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378484"},{"key":"ref38","author":"mohanty","year":"2008","journal-title":"Low-Power High-Level Synthesis for Nanoscale CMOS Circuits"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2014.6783307"},{"key":"ref32","first-page":"113","article-title":"A 190 mV supply, 10 MHz, 90 nm CMOS, pipelined sub-threshold adder using variation-resilient circuit techniques","author":"reynders","year":"2011","journal-title":"Proc IEEE Asian Solid State Circuits Conf (A-SSCC)"},{"key":"ref31","doi-asserted-by":"crossref","first-page":"254","DOI":"10.1109\/VDAT.2010.5496737","article-title":"150 mV sub-threshold asynchronous multiplier for low-power sensor applications","author":"crop","year":"2010","journal-title":"Proc Int Symp VLSI Design Autom Test (VLSI-DAT)"},{"key":"ref30","first-page":"2291","article-title":"Low power multiplier design using complementary pass-transistor asynchronous adiabatic logic","volume":"2","author":"kumar","year":"2010","journal-title":"Int J Comput Sci Eng"},{"key":"ref37","year":"2015","journal-title":"University of California Santa Barbara Express Group"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2015.03.010"},{"key":"ref35","author":"engelbrecht","year":"2006","journal-title":"Fundamentals of Computational Swarm Intelligence"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1016\/S0020-0190(02)00447-7"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-84882-254-2"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1002\/ecjc.4430730304"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403631"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1450095.1450129"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2006.77"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.32"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.83"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/s11721-007-0002-0"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1044111.1044115"},{"key":"ref18","article-title":"A novel framework for applying multiobjective GA and PSO based approaches for simultaneous area, delay, and power optimization in high level synthesis of datapaths","volume":"2012","author":"ram","year":"2012","journal-title":"VLSI Design"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/CECNET.2011.5768190"},{"key":"ref28","article-title":"Active hardware metering for intellectual property protection and security","author":"alkabani","year":"2007","journal-title":"Proc 16th USENIX Security Symp"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2007.4397343"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.828122"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1999.782161"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/0-387-25096-4_6"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-8080-9_5"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"354","DOI":"10.1109\/TCSVT.2006.869964","article-title":"Reversible data hiding","volume":"16","author":"ni","year":"2006","journal-title":"IEEE Trans Circuits Syst Video Technol"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/j.patcog.2007.04.013"},{"key":"ref7","author":"cox","year":"2007","journal-title":"Digital Watermarking and Steganography"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1080334.1080338"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1016\/j.compeleceng.2008.06.002"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.896914"},{"key":"ref20","author":"wayner","year":"2009","journal-title":"Disappearing Cryptography Information Hiding Steganography & Watermarking"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.4103\/0256-4602.123116"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2006.270313"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-012-9085-y"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-007-0136-8"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2028166"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44448-3_34"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/ieeexplore.ieee.org\/iel7\/6287639\/7419931\/07448836.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/7419931\/07448836.pdf?arnumber=7448836","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:26:40Z","timestamp":1642004800000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7448836\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"references-count":40,"URL":"https:\/\/doi.org\/10.1109\/access.2016.2552058","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016]]}}}