{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T11:26:22Z","timestamp":1763724382656,"version":"3.37.3"},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/OAPA.html"}],"funder":[{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology, Taiwan","doi-asserted-by":"publisher","award":["MOST 105-2221-E-155 -076"],"award-info":[{"award-number":["MOST 105-2221-E-155 -076"]}],"id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2017]]},"DOI":"10.1109\/access.2017.2690323","type":"journal-article","created":{"date-parts":[[2017,3,31]],"date-time":"2017-03-31T14:44:28Z","timestamp":1490971468000},"page":"5566-5577","source":"Crossref","is-referenced-by-count":2,"title":["Thermal- and Performance-Aware Address Mapping for the Multi-Channel Three-Dimensional DRAM Systems"],"prefix":"10.1109","volume":"5","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0537-9369","authenticated-orcid":false,"given":"Shu-Yen","family":"Lin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jin-Yi","family":"Lin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Xilinx Spartan-6 FPGA","year":"2016","key":"ref31"},{"journal-title":"Chip Implementation Center","year":"2016","key":"ref30"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859620"},{"journal-title":"Hybrid Memory Cube Micron","year":"2016","key":"ref11"},{"key":"ref12","first-page":"496","article-title":"A 1.2 V 12.8 GB\/s 2 Gb mobile wide-I\/O DRAM with \n$4\\times128$\n I\/Os using TSV-based stacking","author":"kim","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref13","first-page":"713","article-title":"Thermal-aware architecture and mapping for multi-channel three-dimensional DRAM systems","author":"lin","year":"2014","journal-title":"Proc IEEE 3rd Global Conf Consum Electron (GCCE)"},{"key":"ref14","first-page":"611","article-title":"Analysis and runtime management of 3D systems with stacked DRAM for boosting energy efficiency","author":"meng","year":"2012","journal-title":"Proc Design Autom Test Eur Conf Exhibition (DATE)"},{"journal-title":"Micro-ARchitectural and System Simulator for x86-based Systems (MARSSx86)","year":"2016","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164731"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242474"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2235125"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357085"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2742060.2742070"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2013.6523594"},{"key":"ref27","first-page":"352","article-title":"Temperature- and bus traffic-aware data placement in 3D-stacked cache","author":"lee","year":"2010","journal-title":"Proc IEEE\/IFIP VLSI Syst Chip Conf (VLSI-SoC)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228477"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2501626.2512457"},{"journal-title":"Memory Systems Cache DRAM Disk","year":"2007","author":"jacob","key":"ref29"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657041"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2380445.2380467"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TENCONSpring.2013.6584424"},{"key":"ref2","article-title":"Thermal issues of 3D ICs","author":"fukushima","year":"2007","journal-title":"Proc DFR"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763068"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2591513.2591529"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2014.6948903"},{"key":"ref21","first-page":"281","article-title":"Energy optimization in 3D MPSoCs with wide-I\/O DRAM using temperature variation aware bank-wise refresh","author":"sadri","year":"2014","journal-title":"Proc Conf Design Autom Test Eur"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2311798"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2011.5770786"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2010.5617465"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2010.50"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/7859429\/07891039.pdf?arnumber=7891039","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:30:02Z","timestamp":1641987002000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7891039\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":31,"URL":"https:\/\/doi.org\/10.1109\/access.2017.2690323","relation":{},"ISSN":["2169-3536"],"issn-type":[{"type":"electronic","value":"2169-3536"}],"subject":[],"published":{"date-parts":[[2017]]}}}