{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T20:17:41Z","timestamp":1740169061591,"version":"3.37.3"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/OAPA.html"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China (General Program)","doi-asserted-by":"publisher","award":["61274133"],"award-info":[{"award-number":["61274133"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2017]]},"DOI":"10.1109\/access.2017.2701406","type":"journal-article","created":{"date-parts":[[2017,5,4]],"date-time":"2017-05-04T14:12:54Z","timestamp":1493907174000},"page":"7205-7215","source":"Crossref","is-referenced-by-count":4,"title":["Cache Coherence Scheme for HCS-Based CMP and Its System Reliability Analysis"],"prefix":"10.1109","volume":"5","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6557-262X","authenticated-orcid":false,"given":"Sizhao","family":"Li","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Donghui","family":"Guo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2007.898572"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1587\/transinf.2014EDL8094"},{"journal-title":"System reliability theory Models statistical methods and applications","year":"2004","author":"rausand","key":"ref30"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2014.05.003"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/24.52622"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2007.375263"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2002.804736"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1587\/transinf.E96.D.1914"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICMSS.2010.5576958"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2013.12.003"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/SERE-C.2014.47"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/S0191-2615(99)00002-8"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1023\/A:1020941400807"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2007.35"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/2.55497"},{"journal-title":"AMD64 Architecture Programmer&#x2019;s Manual Volume 2 System Program-ming","year":"2013","key":"ref27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/10722167_8"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/71.139202"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TSMCA.2006.889475"},{"key":"ref5","first-page":"997","article-title":"Comparison of memory write policies for NoC based multicore cache coherent systems","author":"de massas","year":"2008","journal-title":"Proc Design Autom Test Eur (DATE)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1594835.1504196"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1217935.1217959"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2011.11"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/12.752662"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2010.43"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TR.1985.5222114"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.237"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/136035.136043"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.20"},{"journal-title":"The Cache Memory Book","year":"1998","author":"handy","key":"ref23"},{"key":"ref26","first-page":"348","article-title":"A low-overhead coherence solution for multiprocessors with private cache memories","author":"papamarcos","year":"1983","journal-title":"Proc Ann Int Symp Comput Archit (ISCA)"},{"key":"ref25","first-page":"124","article-title":"Using cache memory to reduce processor-memory traffic","author":"goodman","year":"1984","journal-title":"Proc Ann Int Symp Comput Archit (ISCA)"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/7859429\/07919147.pdf?arnumber=7919147","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:30:06Z","timestamp":1641987006000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7919147\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":32,"URL":"https:\/\/doi.org\/10.1109\/access.2017.2701406","relation":{},"ISSN":["2169-3536"],"issn-type":[{"type":"electronic","value":"2169-3536"}],"subject":[],"published":{"date-parts":[[2017]]}}}