{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T20:17:27Z","timestamp":1740169047187,"version":"3.37.3"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/OAPA.html"}],"funder":[{"DOI":"10.13039\/501100003977","name":"Israel Science Foundation","doi-asserted-by":"publisher","award":["923\/16"],"award-info":[{"award-number":["923\/16"]}],"id":[{"id":"10.13039\/501100003977","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003977","name":"Israel Science Foundation","doi-asserted-by":"publisher","award":["1868\/16"],"award-info":[{"award-number":["1868\/16"]}],"id":[{"id":"10.13039\/501100003977","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2017]]},"DOI":"10.1109\/access.2017.2766243","type":"journal-article","created":{"date-parts":[[2017,11,2]],"date-time":"2017-11-02T19:39:11Z","timestamp":1509651551000},"page":"24797-24809","source":"Crossref","is-referenced-by-count":5,"title":["A Survey of the Sensitivities of Security Oriented Flip-Flop Circuits"],"prefix":"10.1109","volume":"5","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5591-5799","authenticated-orcid":false,"given":"Itamar","family":"Levi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Netanel","family":"Miller","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Elad","family":"Avni","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Osnat","family":"Keren","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alexander","family":"Fish","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1049\/el.2017.2415"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2001.945371"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2041376"},{"key":"ref12","first-page":"403","article-title":"A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards","author":"tiri","year":"2002","journal-title":"Proc 28th Eur Solid-State Circuits Conf (ESSCIRC)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/4.845191"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1999.759251"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.859586"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2011.0345"},{"article-title":"Dual rail dynamic flip-flop with single evaluation path","year":"2001","author":"amir","key":"ref17"},{"key":"ref18","first-page":"232","article-title":"Three-phase dual-rail pre-charge logic","author":"bucci","year":"2006","journal-title":"Proc Workshop Cryptographic Hardware Embedded Syst"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2165862"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2592967"},{"key":"ref4","first-page":"16","article-title":"Correlation power analysis with a leakage model","author":"brier","year":"2004","journal-title":"Cryptographic Hardware and Embedded Systems&#x2014;CHES"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2452371"},{"journal-title":"Power Analysis Attacks Revealing the Secrets of Smart Cards","year":"2007","author":"mangard","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2000.836791"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2278350"},{"article-title":"Globally-asynchronous locally-synchronous systems","year":"1984","author":"chapiro","key":"ref5"},{"article-title":"Information leakage of flip-flops in DPA-resistant logic styles","year":"2008","author":"moradi","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20050210"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2002.1004593"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.753687"},{"article-title":"Side-channel attacks: Ten years after its publication and the impacts on cryptographic module security testing","year":"2005","author":"zhou","key":"ref1"},{"key":"ref20","volume":"2","author":"rabaey","year":"2002","journal-title":"Digital Integrated Circuits"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/4.641690"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1983.1051937"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2257902"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2013.2262015"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/11894063_2"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-74735-2_29"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/7859429\/08094119.pdf?arnumber=8094119","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T02:59:42Z","timestamp":1633921182000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8094119\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":30,"URL":"https:\/\/doi.org\/10.1109\/access.2017.2766243","relation":{},"ISSN":["2169-3536"],"issn-type":[{"type":"electronic","value":"2169-3536"}],"subject":[],"published":{"date-parts":[[2017]]}}}